A flexible and low-cost menagement technology is desired for fabrication line of both ASICs and cutting edge LSIs. To meet such desire, a management technology named "super operator shifts" has been proposed. After taking operator's skill level into consideration, an ASIC line manager can stretch line working time by use of the super operator shifts. It results that he can successfully get 3-shifts turn around time for severe-delivery-date lots with a payment equal to about 2-shifts line-cost.

A scalable and flexible ASIC CIM system distributed on UNIX workstations, ORCHARD , has been developed. It is designed from three viewpoints: (1) cost and TAT reduction in system construction, (2) flexibility in data management for quality control, and (3) precise and quick scheduling and effective lot tracking to control TAT for each lot. The concept of a "virtual machine" is introduced to connect equipment having various protocols to a host system. The virtual machine is automatically generated at an average automatic generation ratio of as high as 89%, which leads to a reduction in cost and TAT in system construction. Data for quality control is managed by changing flexibly the "data processing recipe." This recipe defines screen format, data collected from equipment, and data transfered from various databases. Precise scheduling of lots with various levels of priority is achieved by introducing a priority evaluation function, thereby reducing scheduling time to 1/20 that for manual scheduling.

An on-line scheduler for ASIC manufacturing line management has been developed. The parameters in the schedule models and the dynamic priority curve in the schedule algorithm were adjusted to obtain schedules well-suited to practical ASIC line management and control. The scheduler is connected to the user interface control module of our ASIC CIM system. In order to facilitate on-line scheduling, we clarify the performance requirements of the computer used for the scheduler with respect to the line scale. Using a current EWS, the scheduler can easily make a one-day schedule for a small-scale line with an annual throughput of less than 1,000 lots within 10 minutes. To cope with larger-scale lines, the multiple scheduling method allows schedules to be produced quickly and efficiently. Therefore, the scheduler can respond flexibly to changes in production plan and line resources and the control delivery date of each lot.

For a CBR (Constant Bit Rate) connection in an ATM (Asynchronous Transfer Mode) network, we determine the CDV (Cell Delay Variation) tolerance for the mapping of ATM cells from the ATM Layer onto the Physical Layer. Our result will be useful to properly allocate resources to connections and to accurately enforce the contract governing the user's cell traffic by UPC (Usage Parameter Control).

An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.

A simple numerical method for calculating paths of creeping rays around an arbitrary convex object is presented. The adventage of this method is that the path of creeping ray is iteratively determined from initial values of incident point and incident direction of the creeping ray without solving differential equation of geodesic path. As the numerical examples, the path of creeping ray on the prolate spheroid and the resonance path of natural modes are shown.

We have systematically grown and characterized (Bi, Pb)2Sr2CaCu2Oy (BPSCCO) single crystals, and investigated the tunneling properties and the intrinsic Josephson effects of the single crystals as a function of the nominal composition of Pb, x. It was observed that Pb atoms (ions) were monotonically substituted for Bi atoms (ions) in the (Bi, Pb)-O layers of the crystals with increasing x in a region of 0x0.5, while the modulation structure was maintained in a range of 0x0.3, but disappeared in x0.3, accompanying the decrease of c-lattice parameter and Tc. Moreover, it was found that the energy gaps Δ of BPSCCO depend hardly on x for x0.5, which are about 24 meV, so that the Pb-induced electronic change in the (Bi, Pb)-O layer do not perturb the electronic states in this superconducting system. And it was confirmed that the currentvoltage characteristics of the BPSCCO single crystals had multiple resistive branches corresponding to a series array of several hundreds Josephson junctions, and showed Shapiro steps and zero-crossing steps with the voltage separation of the order of mV resulting from the phase locking of about a hundred Josephson junctions among them under microwave irradiation. The estimated number of junctions gave the concept that the intrinsic Josephson junctions consist of the superconducting block layers and the insulating layers in the BPSCCO single crystals.

A new superresolution technique is proposed for antenna pattern measurements. Unwanted reflected signals often impinge on the antenna when we measure it outdoors. A time-domain superresolution technique (a MUSIC algorithm) has been proposed to eliminate the unwanted signal for a narrow pass-band antenna. The MUSIC algorithm needs many snapshots to obtain a correlation matrix. This is not preferable for antenna pattern measurements because it takes a long time to obtain the data. In this paper, we propose to reduce a noise component (stochastic quantity) using the FFT and gating techniques before we apply the MUSIC. The new technique needs a few snapshots and saves the measurement time.

In this paper, we propose a polynomial time algorithm for computing the expected maximum number of vertex-disjoint s-t paths in a probabilistic basically series-parallel directed graph and a probabilistic series-parallel undirected graph with distinguished source s and sink t(st), where each edge has a mutually independent failure probability and each vertex is assumed to be failure-free.

This paper describes a vision system, which is based on ASIC (Application Specific Integrated Circuit) approaches, for vehicle guidance on highways. After reviewing related work in the field of intelligent vehicles, stereo vision, and ASIC-based approaches, the paper focuses on a stereo vision system developed for intelligent cruise control. The system measures the distance to the vehicle in front using trinocular triangulation. Application specific processor architectures were developed for low mass-production cost, real-time operation, low power consumption, and small physical size. The system was installed in a trunk of a car and evaluated successfully on highways.

Fuzzy control is suitable for automotive control, because fuzzy control achieves controllability as good as control by humankind. However, since automotive control requires milli-second response and learning control, and the fuzzy system in automobiles requires fewer components (built-in type), a custom fuzzy inference LSI is needed for automotive control. We then indicated requirements of a fuzzy inference LSI suitable for automotive control and fabricated a fuzzy inference LSI using 1.5 µm CMOS process technique. This fabricated fuzzy LSI is designed to utilize in various automotive control experiments such as engine control, cruise control, brake control and steering control. The number of input variables is six, the number of output variables is two, the maximum number of production rules is 256, and the inference time is 63 microseconds (under the condition of six inputs, two outputs and 256 rules). The features of the fuzzy LSI are high speed inference, a built-in type, learning control ability and a memory structure separating into a rule memory and a membership function memory. A fuzzy control system is implemented only by the addition of two devices: the fuzzy LSI and an EPROM. The fuzzy LSI was applied to a rough road durability test aiming at the automatic driving equivalent to the human driver operation. In the test, fuzzy control and linear control were compared in terms of the compensation steering degrees. Linear steering control had a high rate of compensation steering of less than thirty degrees. On the other hand, the accumulated steering compensation of less than twenty degrees in the fuzzy control was about one third that in the linear control. The fuzzy steering control had the same steering compensations as that of human steering. The fuzzy LSI fabricated for various experiments is too large (10.7 mm10.9 mm) to adopt as automotive parts. Therefore, we studied a smaller-sized fuzzy LSI by limiting functions, by changing the parallel processing into sequential processing and by thinning out the memory data of input membership functions. The number of input variables is four, the number of output variables is two, the maximum number of production rules is 160 and the expected inference time is 140 micro-seconds (in the worst case). The obtained chip is small enough (4.8 mm4.8 mm) for automotive applications. Since the chip contains all the memories that are needed to execute fuzzy inference, the chip can be built in a microprocessor as a fuzzy inference co-processor without any other circuits.

This paper describes our recent developments of ASICs for automotive multiplexing and data communications to implement in-vehicle networks. With the advancement of automotive electronics, there are ever growing needs for in-vehicle networks. One need is associated with solving the problem of an increasing number of electrical signal wires that inevitably accompany the increasing applications of automotive electronics. Another kind of need is concerned with sharing vehicle control data among several electronic control units such as engine, brake, suspension, and steering electronic control units to achieve an integrated vehicle control system for the purpose of obtaining higher performances in vehicle dynamics. In order to reduce the number of signal wires and share the control data, in-vehicle networks based on multiplexing and data communications are required. In this paper, two original communication protocols are presented to respectively cover low- and highi-speed multiplexing and data communications that are two most needed communication speed areas in our present and future automobiles. ASICs for the presented communication protoclos were designed and fabricated, using 2 µm COMS process. They have the chip size of 3.2 mm2.7 mm with 5,000 transistors and 6.9 mm4.9 mm with 18,000 transistors respectively for low- and high-speed multiplexing and data communications. An elaborate bus driver/receiver ASIC required for high-speed multiplexing and data communications was also designed and fabricated, using 35 V DC bipolar process. As one of its distinctive features, it can greatly suppress radio frequency noise radiated from a communication bus. It has the chip size of 4.8 mm3.8 mm that contains 570 device elements. The features of the protocols are given in detail with the descriptions of the developed ASICs.

With the evolution of semiconductor technology, automotive electronics has made tremendous progress. The aim of automotive electronics is to improve the basic automotive functions of vehicles (running, turning, and stopping) from the standpoint of environmental protection, energy conservation, and transportation efficiency. This paper introduces the process of automotive electronics with an emphasis on major control systems such as engines and brakes. The role of ASICs in automotive control systems is also presented with actual examples of ASICs that are used in these systems.

It was more than 10 years ago that the first map navigation system, as an example of invehicle information system, has appeared in the market in Japan. Today's navigation system has been improved to the level that the latest system has 10 micro-processors, 7 MBytes of memories, and 4 GBytes of external data storage for map database. From the viewpoint of the automobile driver, there are still some problems with the system. Major problems in general are a lack of traffic information, better human interface, and a need for cost-reduction. The introduction of application specific ICs (ASICs) is expected to make systems smaller, costless, and give higher speed response. Today's in-vehicle information systems are reviewed function by function to discover what functions need to be implemented into ASICs for future systems, what ASICs will be required, and what technology has to be developed. It is concluded that more integration technology is expected including high parformance CPUs, large capacity memories, interface circuits, and some analog circuits such as DA converter. To develop this technology, some, major problems such as power consumption, number of input/output signals, as well as design aid and process technology are pointed out.

We deal with a new type ceramic emitter which is used in a cleanroom ionizer system and is composed of a needle-shaped silicon and a rod-shaped silicon carbide ceramics. The discharge test was carried out to investigate the particle generation from the emitter and the degradation of the emitter. As a result, it was found that the ceramic emitter had practically higher performance than a conventional tungsten emitter.

New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.

This paper discusses methods and numerical simulations of one and two dimensional profilings for an arbitrary convex conducting target using the electromagnetic backscattering. The inversions for profile reconstructions are based upon the modified extended physical optics method (EPO). The modified EPO method assumes the modified physical optics current properly over the entire surface of conducting scatterers. First, the cross sectional area along a line of sight is reconstructed by performing iteratively the Fourier transform of the backscattering field in the frequency domain. Second, the two dimensional profile is reconstructed by synthesizing the above one dimensional results for several incident angles. Numerical simulation results of the target profiling are shown for spheroids and cone-spheroid.

We developed programmable high-performance and high-speed neurocomputer for a large neural network using ASIC neurocomputing chips made by CMOS VLSI technology. The neurocomputer consists of one master node and multiple slave nodes which are connected by two data paths, a broadcast bus and a ring bus. The nodes are made by ASIC chips and each chip has plural nodes in it. The node has four types of computation hardware that can be cascaded in series forming a pipeline. Processing speed is proportional to the number of nodes. The neurocomputer is built on one printed circuit board having 65 VLSI chips that offers 1.5 billion connections/sec. The neurocomputer uses SIMD for easy programming and simple hardware. It can execute complicated computations, memory access and memory address control, and data paths control in a single instruction and in a single time step using the pipeline. The neurocomputer processes forward and backward calculations of multilayer perceptron type neural networks, LVQ, feedback type neural networks such as Hopfield model, and any other types by programming. To compute neural computation effectively and simply in a SIMD type neurocomputer, new processing methods are proposed for parallel computation such as delayed instruction execution, and reconfiguration.

A superresolution technique is considered for use in antenna gain measurements. A modification of the MUSIC algorithm is employed to resolve incident signals separately in the time domain. The modification involves preprocessing the received data using a spatial scheme prior to applying the MUSIC algorithm. Interference rejection in the antenna measurements using the fast Fourier transform (FFT) based techniques have been realized by a recently developed vector network analyzer, and its availability has been reported in the literature. However, response resolution in the time domain of these conventional techniques is limited by the antenna bandwidth. The MUSIC algorithm has the advantage of being able to eliminate unwanted responses when performing antenna measurements in situations where the antenna band-width is too narrow to support FFT based techniques. In this paper, experimental results of antenna gain measurements in a multipath environment show the accuracy and resolving power of this technique.

Selective epitaxial growth technology has been extended to the base formation of a transistor on the basis of the SATURN (Self-Alignment Technology Utilizing Reserved Nitride) process, a high-speed bipolar LSI processing technology. The formation of a self-aligned base contact, coupled with SIC (Selective Ion-implanted Collector) fabricated by lowenergy ion implantation, has not only narrowed the transistor active regions but has drastically reduced the base width. A final base width of 800 and a maximum cut-off frequency of 31 GHz were achieved.