Various mixed-signal very-high-speed integrated circuits have been developed using InP DHBTs. These circuits have been designed for fiber-optic 43 Gbit/s transmissions applications. They include: on the transmitting side, a clocked driver and an EAM driver, as well as a PSBT/DQPSK precoder; on the receiving side, a sensitive decision circuit, a limiting amplifier and an eye monitor. System experiments made possible by these circuits include a 6 Tbit/s transmission on >6000 km distance.

We investigated physical conditions for optimum display systems on various TV viewing conditions, and found that visual brightness function could be derived from relationships between Steven's power law and Bartleson-Breneman's brightness function, and that the optimum physical contrast ratio and compensated gamma for display system with adaptation luminance level could be obtained from the proposed brightness function.

To detect lung area, this paper proposes curve stopping function that is based on CT coefficient of area of lung parenchyma instead of existing edge indication function. The proposed method was compared numerically using various measures and this method can detect better lung parenchyma region than existing methods. In addition, detecting procedure of the area of lung parenchyma was visually verified in lung images.

In this letter, we propose a combined scheme of minimum mean square error (MMSE) detection and successive interference cancellation (SIC) for multiuser space-time block coded orthogonal frequency division multiplexing (STBC-OFDM) systems. With the same complexity order, the proposed scheme provides significant bit error rate (BER) performance improvement over the linear MMSE multiuser detector.

In this letter, we discussed some properties of characteristic generators for a finite Abelian group code, proved that any two characteristic generators can not start (end) at the same position and have the same order of the starting (ending) components simultaneously, and that the number of all characteristic generators can be directly computed from the group code itself. These properties are exactly the generalization of the corresponding trellis properties of a linear code over a field.

Hardware prototyping has been widely used for ASIC/SoC verification. This paper proposes a new hardware design verification method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or even weeks, without a break. It compresses the captured data in real time and stores it in a state transition format in memory. Since it records all the transitions, it is effective in finding and fixing errors, even ones that occur rarely or intermittently. It can also be programmed to generate a trigger for a logic analyzer when it detects certain transitions. This is useful for debugging situations where the engineer has trouble finding an appropriate trigger condition to pinpoint the source of errors. We have been using the method in hardware prototyping for ASIC/SoC development for two years and found it useful for system level tests, and in particular for long running tests.

A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.

Temperature-tracking is becoming of paramount importance in modern electronic design automation tools. In this paper, we present a deterministic thermal placement algorithm for standard cell based layout which can lead to a smooth temperature distribution over the die. It is mainly based on Fiduccia-Mattheyses partition scheme and a former substrate thermal model that can convert the known temperature constraints into the corresponding power distribution constraints. Moreover, a kind of force-directed heuristic based on cells' power consumption is introduced in the above process. Experimental results demonstrate a comparatively uniform temperature distribution and show a reduction of the maximal temperature on the die.

This paper shows that the Surrounding Gate Transistor (SGT) can be scaled down to decananometer gate lengths by using an intrinsically-doped body and gate work function engineering. Strong gate controllability is an essential characteristics of the SGT. However, by using an intrinsically-doped body, the SGT can realize a higher carrier mobility and stronger gate controllability of the silicon body. Then, in order to adjust the threshold voltage, it is necessary to adopt gate work function engineering in which a metal or metal silicide gate is used. Using a three-dimensional (3D) device simulator, we analyze the short-channel effects and current characteristics of the SGT. We compare the device characteristics of the SGT to those of the Tri-gate transistor and Double-Gate (DG) MOSFET. When the silicon pillar diameter (or silicon body thickness) is 10 nm, the gate length is 20 nm, and the oxide thickness is 1 nm, the SGT shows a subthreshold swing of 63 mV/dec and a DIBL of -17 mV, whereas the Tri-gate transistor and the DG MOSFET show a subthreshold swing of 71 mV/dec and 77 mV/dec, respectively, and a DIBL of -47 mV and -75 mV, respectively. By adjusting the value of the gate work function, we define the off current at VG = 0 V and VD = 1 V. When the off current is set at 1 pA/µm, the SGT can realize a high on current of 1020 µA/µm at VG = 1 V and VD = 1 V. Moreover, the on current of the SGT is 21% larger than that of the Tri-gate transistor and 52% larger than that of the DG MOSFET. Therefore, the SGT can be scaled reliably toward the decananometer gate length for high-speed and low-power ULSI.

A dielectric resonator with a gap between the top plate and the rest has been useful for measuring the penetration depth (λ) of superconductor films, a parameter essential for obtaining the intrinsic microwave surface resistance (Rs) of thin superconductor films. We investigated effects of a gap on the microwave properties of TE0ml-mode sapphire resonators with a gap between the top plate and the rest of the resonator. Regardless of a 10 µm-gap in TE0ml-mode sapphire resonators, variations of the TE0ml-mode resonant frequency on temperature (Δf0) as well as TE0ml-mode unloaded Q remained almost the same due to lack of axial currents inside the resonator and negligible radiation effects. The λ of YBa2Cu3O7-δ (YBCO) films obtained from a fit to the temperature-dependent Δf0 appeared to be 195 nm at 0 K and 19.3 GHz, which was well compared with the corresponding value of 193 nm at 10 kHz measured by the mutual inductance method. The intrinsic Rs of YBCO films on the order of 1 mΩ, and the tan δ of sapphire on the order of 10-8 at 15 K and 40 GHz could be measured simultaneously using sapphire resonators with a 10 µm-gap.

The IETF (Internet Engineering Task Force) has developed a Network Mobility (NEMO) basic support protocol by extending the operation of Mobile IPv6 to provide uninterrupted Internet connectivity to the communicating nodes of mobile networks. The protocol uses a mobile router (MR) in the mobile network to perform prefix scope binding updates with its home agent (HA) to establish a bi-directional tunnel between the HA and MR. This solution reduces location-update signaling by making network movements transparent to the mobile nodes behind the MR. However, delays in data delivery and higher overheads are likely to occur because of sub-optimal routing and multiple encapsulation of data packets. To resolve these problems, we propose a mobile router-assisted route optimization (MoRaRo) scheme for NEMO support. With MoRaRo, a mobile node performs route optimization with a correspondent node only once, at the beginning of a session. After that the MR performs route optimization on behalf of all active mobile nodes when the network moves. The virtue of this scheme is that it requires only slight modification of the implementation of the NEMO basic support protocol at local entities such as the MR and mobile nodes of the mobile network, leaving entities in the core or in other administrative domains untouched. MoRaRo enables a correspondent node to forward packets directly to the mobile network without any tunneling, thus reducing packet delay and encapsulation overheads in the core network. To enable the scheme to be evaluated, we present the results of both theoretical analysis and simulation.

Automatic discovery of physical topology plays a crucial role in enhancing the manageability of modern large Ethernet mesh networks. Despite the importance of the problem, earlier research and commercial network management tools have typically concentrated on either discovering active topology, or proprietary solutions targeting specific product families. Recent works [1]-[3] have demonstrated that physical topology can be determined using standard SNMP MIB, but these algorithms depend on Filtering Database and rely on the so-called spanning tree protocol (IEEE 802.1d) in order to break cycles, thereby avoiding the possibility of infinitely circulating packets and deadlocks. A previous work [1] requires that Filtering Database entries are completed; however it is a very critical assumption in a realistic Ethernet mesh network. In this paper, we have proposed a new topology discovery algorithm which works without the complete knowledge of Filtering Database. Our algorithm can discover complete physical topology including inactive interfaces eliminated by the spanning tree protocol in LEMNs. The effectiveness of the algorithm is demonstrated by an implementation.

There is redundancy in instruction sequences, which can be utilized for information hiding or digital watermarking. This study quantitatively examines the information capacity in the order of variables, basic blocks, and instructions in each basic block. Derived information density was 0.3% for reordering of basic blocks, 0.3% for reordering instructions in basic blocks, and 0.02% for reordering of global variables. The performance degradation caused by this method was less than 6.1%, and the increase in the object file size was less than 5.1%.

This paper describes a method for estimating the amplitude characteristics of poles common to multiple room transfer functions from musical audio signals received by multiple microphones. Knowledge of these pole characteristics would make it easier to manipulate audio equalizers, since they correspond to the room resonance. It has been proven that an estimate of the poles can be calculated precisely when a source signal is white. However, if a source signal is colored as in the case of a musical audio signal, the estimate is degraded by the frequency characteristics originally contained in the source signal. In this paper, we consider that an amplitude spectrum of a musical audio signal consists of its envelope and fine structure. We assume that musical pieces can be classified into several categories according to their average amplitude spectral envelopes. Based on this assumption, the amplitude spectral envelope of the musical audio signal can be obtained from prior knowledge of the average amplitude spectral envelope of a musical piece category into which the target piece is classified. On the other hand, the fine structure is identified based on its time variance. By removing both the spectral envelope and the fine structure from the amplitude spectrum estimated with the conventional method, the amplitude characteristics of the acoustical poles can be extracted. Simulation results for 20 popular songs revealed that our method was capable of estimating the amplitude characteristics of the acoustical poles with a spectral distortion of 3.11 dB. In particular, most of the spectral peaks, corresponding to the room resonance modes, were successfully detected.

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

Pattern extraction is an indispensable step in bare printed circuit board (PCB) inspection and plays an important role in automatic inspection system design. A good approach for pattern definition and extraction will make the following PCB diagnosis easy and efficient. The window-based technique has great potential in PCB patterns extraction due to its simplicity. The conventional window-based pattern extraction methods, such as Small Seeds Window Extraction method (SSWE) and Large Seeds Window Extraction method (LSWE), have the problems of losing some useful copper traces and splitting slanted-lines into too many small similar windows. These methods introduce the difficulty and computation intensive in automatic inspection. In this paper, a novel method called Contour Based Window Extraction (CBWE) algorithm is proposed for improvement. In comparison with both SSWE and LSWE methods, the CBWE algorithm has several advantages in application. Firstly, all traces can be segmented and enclosed by a valid window. Secondly, the type of the entire horizontal or vertical line of copper trace is preserved. Thirdly, the number of the valid windows is less than that extracted by SSWE and LSWE. From the experimental results, the proposed CBWE algorithm is demonstrated to be very effective in basic pattern extraction from bare PCB image analysis.

Incremental modification and optimization in VLSI physical design is of fundamental importance. Based on the O-tree (ordered tree) representation which has more prominent advantages in comparison with other topological representations of non-slicing floorplans, in this paper, we present an incremental placement algorithm for BBL (Building Block Layout) design in VLSI physical design. The good performance of experimental results in dealing with some instances proves the effectiveness of our algorithm.

The Modified edge representation (MER) is the concept to be used in the line integral approximation for computing the surface radiation integrals of diffraction. The MER as applied to the physical optics (PO-MER), has remarkable accuracy in the surface-to-line integral reduction even for the curved surfaces and for sources very close to the scatterer. In the discussion of the mathematical foundation for this accuracy, the evaluation of the singularities in the integrand of the PO-MER line integration was left for further study.

Locality in high frequency diffraction is embodied in the Method of Moments (MoM) in view of the method of stationary phase. Local-domain basis functions accompanied with the phase detour, which are not entire domain but are much larger than the segment length in the usual MoM, are newly introduced to enhance the cancellation of mutual coupling over the local-domain; the off-diagonal elements in resultant reaction matrix evanesce rapidly. The Fresnel zone threshold is proposed for simple and effective truncation of the matrix into the sparse band matrix. Numerical examples for the 2-D strip and the 2-D corner reflector demonstrate the feasibility as well as difficulties of the concept; the way mitigating computational load of the MoM in high frequency problems is suggested.

This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.