We reported a secure scan design approach using shift register equivalents (SR-equivalents, for short) that are functionally equivalent but not structurally equivalent to shift registers [10 and also introduced generalized shift registers (GSRs, for short) to apply them to secure scan design [11]-[13]. In this paper, we combine both concepts of SR-equivalents and GSRs and consider the synthesis problem of SR-equivalent GSRs, i.e., how to modify a given GSR to an SR-equivalent GSR. We also consider the enumeration problem of SR-equivalent GFSRs, i.e., the cardinality of the class of SR-equivalent GSRs to clarify the security level of the secure scan architecture.

This paper describes a numerical assessment methodology of pacemaker EMI triggered by HF-band wireless power transfer system. By using three dimensional full-wave numerical simulation based on finite element method, interference voltage induced at the connector of the pacemaker inside the phantom that is used for in-vitro EMI assessment is obtained. Simulated example includes different exposure scenarios in order to estimate the maximum interference voltage.

Ternary content addressable memory (TCAM), which can store 0, 1, or X in its cells, is widely used to store routing tables in network routers. Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI), which increase Vth and degrade transistor switching speed, have become major reliability challenges. This study analyzes the signal probability of routing tables. The results show that many cells retain static stress and suffer significant degradation caused by NBTI and PBTI effects. The bit flipping technique is improved and proactive power gating recovery is proposed to mitigate NBTI and PBTI effects. In order to maintain the functionality of TCAM after bit flipping, a novel TCAM cell design is proposed. Simulation results show that compared to the original architecture, the bit flipping technique improves read static noise margin (SNM) for data and mask cells by 16.84% and 29.94%, respectively, and reduces search time degradation by 12.95%. The power gating technique improves read SNM for data and mask cells by 12.31% and 20.92%, respectively, and reduces search time degradation by 17.57%. When both techniques are used, read SNM for data and mask cells is improved by 17.74% and 30.53%, respectively, and search time degradation is reduced by 21.01%.

There have been many previous studies to facilitate the use of smartphones as remote controllers of PCs. Image-based user interfaces have been suggested to provide fully functioning remote applications. However, most previous image-based interfaces consume high battery power and network bandwidth. Also most users have specific preferences on various applications on remote PCs, but previous smartphone interface systems would not allow users to define their own smartphone interfaces to set their preferences. This paper presents a new smartphone user interface system, SmartUI, for remote PC control. SmartUI is designed as a text-oriented web-based interface, so that it can be used on any smartphone with a built-in web browser while saving battery power and network bandwidth. Moreover, SmartUI enables a user to create buttons on a smartphone; for a quick launch and for shortcut keys, associated with a specific remote PC application. As a result, SmartUI allows a user to create his or her own smartphone interface for remote PC control, while saving battery power and network bandwidth. SmartUI has been tested with various smartphones and the results are also presented in this paper.

An efficient three-dimensional (3-D) fundamental locally one-dimensional finite-difference time-domain (FLOD-FDTD) method incorporated with memristor is presented. The FLOD-FDTD method achieves higher efficiency and simplicity with matrix-operator-free right-hand sides (RHS). The updating equations of memristor-incorporated FLOD-FDTD method are derived in detail. Numerical results are provided to show the trade-off between efficiency and accuracy.

A 10-bit 20-MS/s asynchronous SAR ADC with a meta-stability detector using replica comparators is proposed. The proposed SAR ADC with the area of 0.093mm2 is implemented using a 130-nm CMOS process with a 1.2-V supply. The measured peak ENOBs for the full rail-to-rail differential input signal is 9.6bits.

This paper considers an optimal stabilization problem of quantitative discrete event systems (DESs) under the influence of disturbances. We model a DES by a deterministic weighted automaton. The control cost is concerned with the sum of the weights along the generated trajectories reaching the target state. The region of weak attraction is the set of states of the system such that all trajectories starting from them can be controlled to reach a specified set of target states and stay there indefinitely. An optimal stabilizing controller is a controller that drives the states in this region to the set of target states with minimum control cost and keeps them there. We consider two control objectives: to minimize the worst-case control cost (1) subject to all enabled trajectories and (2) subject to the enabled trajectories starting by controllable events. Moreover, we consider the disturbances which are uncontrollable events that rarely occur in the real system but may degrade the control performance when they occur. We propose a linearithmic time algorithm for the synthesis of an optimal stabilizing controller which is robust to disturbances.

Given a set of positive-weighted points and a query rectangle r (specified by a client) of given extents, the goal of a maximizing range sum (MaxRS) query is to find the optimal location of r such that the total weights of all points covered by r is maximized. In this paper, we address the problem of processing MaxRS queries over road network databases and propose two new external memory methods. Through a set of simulations, we evaluate the performance of the proposed methods.

In this paper, we exploit MapReduce framework and other optimizations to improve the performance of hash join algorithms on multi-core CPUs, including No partition hash join and partition hash join. We first implement hash join algorithms with a shared-memory MapReduce model on multi-core CPUs, including partition phase, build phase, and probe phase. Then we design an improved cuckoo hash table for our hash join, which consists of a cuckoo hash table and a chained hash table. Based on our implementation, we also propose two optimizations, one for the usage of SIMD instructions, and the other for partition phase. Through experimental result and analysis, we finally find that the partition hash join often outperforms the No partition hash join, and our hash join algorithm is faster than previous work by an average of 30%.

In our previous work [12], [13], we introduced generalized feed-forward shift registers (GF2SR, for short) to apply them to secure and testable scan design. In this paper, we introduce another class of generalized shift registers called generalized feedback shift registers (GFSR, for short), and consider the properties of GFSR that are useful for secure scan design. We present how to control/observe GFSR to guarantee scan-in and scan-out operations that can be overlapped in the same way as the conventional scan testing. Testability and security of scan design using GFSR are considered. The cardinality of each class is clarified. We also present how to design strongly secure GFSR as well as GF2SR considered in [13].

This paper proposes a novel object tracking method via online boosting. The on-line boosting technique is combined with local features to treat tracking as a keypoint matching problem. First, We improve matching reliability by exploiting the statistical repeatability of local features. In addition, we propose 2D scale-rotation invariant quasi-keypoint matching to further improve matching efficiency. Benefiting from SURF feature's statistical repeatability and the complementary quasi-keypoint matching technique, we can easily find reliable matching pairs and thus perform accurate and stable tracking. Experimental results show that the proposed method achieves better performance compared with previously reported trackers.

In this letter, we propose a novel wear leveling technique we call Hidden cold block-aware Wear Leveling (HaWL) using a bit-set threshold. HaWL prolongs the lifetime of flash memory devices by using a bit array table in wear leveling. The bit array table saves the histories of block erasures for a period and distinguishes cold blocks from all blocks. In addition, HaWL can reduce the size of the bit array table by using a one-to-many mode, where one bit is related to many blocks. Moreover, to prevent degradation of wear leveling in the one-to-many mode, HaWL uses bit-set threshold (BST) and increases the accuracy of the cold block information. The performance results illustrate that HaWL prolongs the lifetime of flash memory by up to 48% compared with previous wear leveling techniques in our experiments.

It is crucial to promote interdisciplinary research and recommend collaborators from different research fields via academic database analysis. This paper addresses a problem to characterize researchers' interests with a set of diverse research topics found in a large-scale academic database. Specifically, we first use latent Dirichlet allocation to extract topics as distributions over words from a training dataset. Then, we convert the textual features of a researcher's publications to topic vectors, and calculate the centroid of these vectors to summarize the researcher's interest as a single vector. In experiments conducted on CiNii Articles, which is the largest academic database in Japan, we show that the extracted topics reflect the diversity of the research fields in the database. The experiment results also indicate the applicability of the proposed topic representation to the author disambiguation problem.

In recent years, society has experienced several changes in its ways and methods of consuming. Nowadays, the diversity and the customization of products and services have provoked that the consumer needs continuously change. Hence, the database systems support e-business processes are required to be timeliness and adaptable to the changing preferences. Autonomous Decentralized Database System (ADDS), has been proposed in order to satisfy the enhanced requirements of current on-line e-business applications. Autonomy and decentralization of subsystems help to achieve short response times in highly competitive situations and an autonomous Coordination Mobile Agent (CMA) has been proposed to achieve flexibility in a highly dynamic environment. However, a problem in ADDS is as the number of sites increases, the distribution and harmonization of product information among the sites are turning difficult. Therefore, many users cannot be satisfied quickly. As a result, system timeliness is inadequate. To solve this problem, a self configuration technology is proposed. This technology can configure the system to the evolving situation dynamically for achieving high response. A simulation shows the effectiveness of the proposed technology in a large-scale system. Finally, an implementation of this technology is presented.

We design a new hash table for high-speed networking that reduces main memory accesses even when the ratio of inserted items to the table size is high, at which point previous schemes no longer work. This improvement comes from a new design of a summary, called expanded keys, exploiting recent multiple hash functions and Bloom filter theories.

Patch clamp measurement technique is one of the most important techniques in the field of electrophysiology. The elucidation of the channels, nerve cells, and brain activities as well as contribution of the treatment of neurological disorders is expected from the measurement of ion current. A current-to-voltage converter, which is the front end circuit of the patch clamp measurement system is fabricated using 0.18µm CMOS technology. The current-to-voltage converter requires a resistance as high as 50MΩ as a feedback resistor in order to ensure a high signal-to-noise ratio for very small signals. However, the circuit becomes unstable due to the large parasitic capacitance between the poly layer and the substrate of the on-chip feedback resistor and the instability causes the peaking at lower frequency. The instability of a current-to-voltage converter with a high-resistance as a feedback resistor is analyzed theoretically. A compensation circuit to stabilize the amplifier by driving the N-well under poly resistor to suppress the effect of parasitic capacitance using buffer circuits is proposed. The performance of the proposed circuit is confirmed by both simulation and measurement of fabricated chip. The peaking in frequency characteristic is suppressed properly by the proposed method. Furthermore, the bandwidth of the amplifier is expanded up to 11.3kHz, which is desirable for a patch clamp measurement. In addition, the input referred rms noise with the range of 10Hz ∼ 10kHz is 2.09 Arms and is sufficiently reach the requirement for measure of both whole-cell and a part of single-channel recordings.

On-chip neural interface devices based on CMOS image sensor technology are proposed and demonstrated. The devices were designed with target applications to optogenetics in bioscience. Multifunctional CMOS image sensors equipped with an addressable on-chip electrode array were integrated with a functional interface chip that contained embedded GaInN light emitting diodes (LEDs) and electrodes to create a neural interface. Detailed design information regarding the CMOS sensor chip and the functional interface chip including the packaging structure and fabrication processes are presented in this paper. The on-chip optical stimulation functionality was demonstrated in an in vitro experiment using neuron-like cells cultured on the proposed device.

In this paper, we formulate an optimal stabilization problem of quantitative discrete event systems (DESs) under partial observation. A DES under partial observation is a system where its behaviors cannot be completely observed by a supervisor. In our framework, the supervisor observes not only masked events but also masked states. Our problem is then to synthesize a supervisor that drives the DES to a given target state with the minimum cost based on the detected sequences of masked events and states. We propose an algorithm for deciding the existence of an optimal stabilizing supervisor, and compute it if it exists.

In this paper, we propose a communication-efficient top-k continuous query processing method on distributed local nodes where data are horizontally partitioned. A designated coordinator server takes the role of issuing queries from users to local nodes and delivering the results to users. The final results are requested via a top-k subscription which lets local nodes know which data and updates need to be returned to users. Our proposed method makes use of the active previously posed queries to identify a small set of needed top-k subscriptions. In addition, with the pre-indexed nodes' skylines, the number of local nodes to be subscribed can be significantly reduced. As a result, only a small number of subscriptions are informed to a small number of local nodes resulting in lower communication overhead. Furthermore, according to dynamic data updates, we also propose a method that prevents nodes from reporting needless updates and also maintenance procedures to preserve the consistency. The results of experiments that measure the volume of transferred data show that our proposed method significantly outperforms the previously proposed methods.

The Lyapunov stability theory-based adaptive filter (LST-AF) is a robust filtering algorithm which the tracking error quickly converges to zero asymptotically. Recently, the software module of the LST-AF algorithm is effectively used in engineering applications such as tracking, prediction, noise cancellation and system identification problems. Therefore, hardware implementation becomes necessary in many cases where real time procedure is needed. In this paper, an implementation of the LST-AF algorithm on Field Programmable Gate Arrays (FPGA) is realized for the first time to our knowledge. The proposed hardware implementation on FPGA is performed for two main benchmark problems; i) tracking of an artificial signal and a Henon chaotic signal, ii) estimation of filter parameters using a system identification model. Experimental results are comparatively presented to test accuracy, performance and logic occupation. The results show that our proposed hardware implementation not only conserves the capabilities of software versions of the LST-AF algorithm but also achieves a better performance than them.