A linear term tree is defined as an edge-labeled rooted tree pattern with ordered children and internal structured variables whose labels are mutually distinct. A variable can be replaced with arbitrary edge-labeled rooted ordered trees. We consider the polynomial time learnability of finite unions of linear term trees in the exact learning model formalized by Angluin. The language L(t) of a linear term tree t is the set of all trees obtained from t by substituting arbitrary edge-labeled rooted ordered trees for all variables in t. Moreover, for a finite set S of linear term trees, we define L(S)=∪t∈S L(t). A target of learning, denoted by T*, is a finite set of linear term trees, where the number of edge labels is infinite. In this paper, for any set T* of m linear term trees (m ≥ 0), we present a query learning algorithm which exactly identifies T* in polynomial time using at most 2mn2 Restricted Subset queries and at most m+1 Equivalence queries, where n is the maximum size of counterexamples. Finally, we note that finite sets of linear term trees are not learnable in polynomial time using Restricted Equivalence, Membership and Subset queries.

This letter deals with computationally efficient maximum-likelihood (ML) detection for the quasi-orthogonal space-time block code (QOSTBC) with four transmit antennas. The proposed ML detector uses a permutation based real-valued equivalent channel matrix representation. As a result, the complexity of ML detection problem is moderated from O(2|A|2) to O(4|A|), where |A| is modulation order. Numerical results show that the proposed ML detector provides ML performance and achieves greatly high computational savings.

We demonstrate a wavelength division multiplexing passive optical network (WDM-PON) based on wavelength-locked Fabry-Perot laser diodes and thin-film filters. Twelve Fast Ethernet signals are bi-directionally transmitted over the multi-branch optical distribution network (ODN). The ODN has distributed branch nodes and bus networks.

This paper presents a new interactive learning method for spoken word acquisition through human-machine audio-visual interfaces. During the course of learning, the machine makes a decision about whether an orally input word is a word in the lexicon the machine has learned, using both speech and visual cues. Learning is carried out on-line, incrementally, based on a combination of active and unsupervised learning principles. If the machine judges with a high degree of confidence that its decision is correct, it learns the statistical models of the word and a corresponding image category as its meaning in an unsupervised way. Otherwise, it asks the user a question in an active way. The function used to estimate the degree of confidence is also learned adaptively on-line. Experimental results show that the combination of active and unsupervised learning principles enables the machine and the user to adapt to each other, which makes the learning process more efficient.

Burn-in is a widely used method to improve the quality of products or systems after they have been produced. In this paper, optimal burn-in procedures for a system with two types of failures (i.e., minor and catastrophic failures) are investigated. A new system surviving burn-in time b is put into field operation and the system is used under a warranty policy under which the manufacturer agrees to provide a replacement system for any system that fails to achieve a lifetime of at least w. Upper bounds for optimal burn-in time minimizing the total expected warranty cost are obtained under a more general assumption on the shape of the failure rate function which includes the bathtub shaped failure rate function as a special case.

We propose and demonstrate a simple one-bus two-ring configuration where the two rings are mutually coupled that has advantages over the one-ring structure. Unlike a one cavity system, it can exhibit near critically-coupled transmission with a broader range of loss. It can also significantly enhance the cavity finesse by simply making the second ring twice the size of the bus-coupled one, with the enhancement proportional to the intensity buildup in the second ring.

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an auto-switching encoder for efficient digital processing is also presented. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28 mm2 in 0.18 µm CMOS technology.

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.

Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). In this letter, a low-power low-noise clock signal generator for ADCs is described. As a clock signal generator, a ring-VCO-based charge pump PLL is used to reduce power dissipation within a given jitter specification. The clock signal generator is fabricated on a CMOS chip with 200-MSPS 10-bit ADC. The measured results show that the ADC keeps a 60-MHz input bandwidth and 53-dB dynamic range and a next-generation mobile wireless terminal can be realized with the ADCs and the on-chip low-power clock generator.

In this review paper we showcase recent activities on silicon photonics science and technology research in Hong Kong regarding two important topical areas--microresonator devices and optical nonlinearities. Our work on silicon microresonator filters, switches and modulators have shown promise for the nascent development of on-chip optoelectronic signal processing systems, while our studies on optical nonlinearities have contributed to basic understanding of silicon-based optically-pumped light sources and helium-implanted detectors. Here, we review our various passive and electro-optic active microresonator devices including (i) cascaded microring resonator cross-connect filters, (ii) NRZ-to-PRZ data format converters using a microring resonator notch filter, (iii) GHz-speed carrier-injection-based microring resonator modulators and 0.5-GHz-speed carrier-injection-based microdisk resonator modulators, and (iv) electrically reconfigurable microring resonator add-drop filters and electro-optic logic switches using interferometric resonance control. On the nonlinear waveguide front, we review the main nonlinear optical effects in silicon, and show that even at fairly modest average powers two-photon absorption and the accompanied free-carrier linear absorption could lead to optical limiting and a dramatic reduction in the effective lengths of nonlinear devices.

The quality of the Side-information frame (S frame) influences significantly the rate-distortion performance in the Distributed Video Coding (DVC). In this letter, we propose an efficient Side-Information Frame Generator (SIFG). It considers smoothness constraints of both the motion vector field and spatial adjacent pixels. Simulation results show that the proposed techniques provide potential rate-distortion performance advantages. Besides, the fine visual quality of the S frame is obtained.

For unitary space-time code (USTC), the impact of spatial correlation on error performance is investigated. A tighter and simpler upper bound is derived for generalized likelihood ratio test decoder. We establish that the spatial correlation does not change the diversity gain, whereas it degrades the error performance of USTC. Motivated by the precoding of space-time block code, we designed a precoder for USTC to handle the case of the joint transmit-receive correlation. Numerical results show that the degradation in performance due to spatial correlation can be considerably compensated by the proposed algorithm.

This paper addresses the problem of maximizing the protocol capacity of 802.11e networks, under the assumption that each access category (AC) has the same packet length. We prove that the maximal protocol capacity can be achieved at an optimal operating point with the medium idle probability of , where Tc* is the duration of collision time in terms of slot unit. Our results indicate that the optimal operating point is independent of the number of stations and throughput ratio among ACs, which means the proposed analytical results still hold even when throughput ratio and station number are time-varying. Further, we show that the maximal protocol capacity can be achieved in saturated cases by properly choosing the protocol parameters. We present a parameter configuration algorithm to achieve both efficient channel utilization and proportional fairness in IEEE 802.11e EDCA networks. Extensive simulation and analytical results are presented to verify the proposed ideas.

In 1997, M. Matsui proposed secret-key cryptosystems called MISTY 1 and MISTY 2, which are 8- and 12-round block ciphers with a 64-bit block, and a 128-bit key. They are designed based on the principle of provable security against differential and linear cryptanalysis. In this paper we present large collections of weak-key classes encompassing 273 and 270 weak keys for 7-round MISTY 1 and 2 for which they are vulnerable to a related-key amplified boomerang attack. Under our weak-key assumptions, the related-key amplified boomerang attack can be applied to 7-round MISTY 1 and 2 with 254, 256 chosen plaintexts and 255.3 7-round MISTY 1 encryptions, 265 7-round MISTY 2 encryptions, respectively.

In case of link failures, many ad hoc routing protocols recover a route by employing source-initiated route re-discovery, but this approach can degrade system performance. Some use localized route recovery, which may yield non-optimal paths. Our proposal provides a mechanism that can enhance the overall routing performance by initiating route recovery at the destination node. We elucidate the effects through simulations including comparisons with AODV and AODV with local repair.

A design of a low-power CMOS ring oscillator for an application to a 13.56 MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, fOSC, to decay of the power supply VDD. By employing a gm-boosting subcircuit, power dissipation is decreased to 49 µW at fOSC=13.56 MHz. The sensitivity of fOSC to VDD is reduced to -0.02 at fOSC=13.56 MHz thanks to the use of composite high-impedance current sources.

In this paper, we present a new extension of the butterfly digraph, which is known as one of the topologies used for interconnection networks. The butterfly digraph was previously generalized from binary to d-ary. We define a new digraph by adding a signed label to each vertex of the d-ary butterfly digraph. We call this digraph the dihedral butterfly digraph and study its properties. Furthermore, we show that this digraph can be represented as a Cayley graph. It is well known that a butterfly digraph can be represented as a Cayley graph on the wreath product of two cyclic groups [1]. We prove that a dihedral butterfly digraph can be represented as a Cayley graph in two ways.

In this paper, an energy-collection-based non-coherent IR-UWB receiver allowing low complexity and low power consumption is proposed for short range data communication. The proposed receiver consists of an on-the-fly integrator, a 1-bit digital sampler, a pre-processor and a digital symbol synchronizer. The on-the-fly integrator for energy collection and the 1-bit digital sampler reduce complexity of IR-UWB system. Furthermore, with a simple digital filter in the pre-processing unit, SNR and robustness of the receiver against time-varying channel are enhanced. Also the receiver complexity is diminished by a simple scheme of symbol synchronization based on rough time information about incoming pulses, not requiring exact timing information. The performance of the proposed receiver is simulated based on IEEE 802.15.4a channel model and the algorithms are implemented and verified on a FPGA.

A low-ripple diode charge-pump type AC-DC converter based on the Cockcroft-Walton diode multiplier is proposed for coil-coupled passive IC tags in this paper. This circuit is developed as a power supply for passive RFID tags with smart functions such as heart rate detection and/or body temperature measurement. The proposed circuit converts wirelessly induced power to a low-ripple DC voltage suitable for a 13.56 MHz RFID tag. The proposed circuit topology and the principle of operation are explained and treated theoretically by using quasi-equivalent small-signal models. The proposed circuit was implemented on a PCB. And it was confirmed that the proposed circuit provides 3.3 V DC with a ripple of less than 20 mV when a 4 Vp-p sinusoidal input is applied. Under this condition, the maximum output power is about 310 µW. The measured results were in good agreement with theoretical and HSPICE simulation results.

In this Letter, we investigate the correlation rate of a random sequence data set which is collected by RFID (Radio Frequency IDentification) readers in an indoor location. Using a passive RFID tag introduces reading error, which causes a loss of original data. From the question of how sensing errors of RFID readers affect the location prediction algorithm used for context awareness services at home, we analyze the correlation rate of a collected data set with respect to RFID reader-sensing error rate. Through our analysis, we conclude that the prediction accuracy can be better or worse than the one of the original data streams according to the error rate. We suggest that the reader specification has to be satisfied by the error boundary which is found in this work for the tolerant location prediction.