In this letter, the influence of the downlink average ratio of the other cell interference to other-user interference in the serving cell (DARI) on the distributed repeater system (DRS) performance is analyzed. It is found that the improvement of DARI depends on a propagation path loss environment. Applying the computed DARI to a 3-RS DRS cell, as high as 13.9% capacity enhancement was obtained when the path loss exponent is 4.5. In addition, by using the power allocation equation, it is expected that a hexagonal DRS cell without coverage holes or excessive coverage overlap can be realized.

Encapsulating critical computation subgraphs as application-specific instruction set extensions is an effective technique to enhance the performance of embedded processors. However, the addition of custom functional units to the base processor is required to support the execution of these custom instructions. Although automated tools have been developed to reduce the long design time needed to produce a new extensible processor for each application, short time-to-market, significant non-recurring engineering and design costs are issues. To address these concerns, we introduce an adaptive extensible processor in which custom instructions are generated and added after chip-fabrication. To support this feature, custom functional units (CFUs) are replaced by a reconfigurable functional unit (RFU). The proposed RFU is based on a matrix of functional units which is multi-cycle with the capability of conditional execution. A quantitative approach is utilized to propose an efficient architecture for the RFU and fix its constraints. To generate more effective custom instructions, they are extended over basic blocks and hence, multiple exits custom instructions are proposed. Conditional execution has been added to the RFU to support the multi-exit feature of custom instructions. Experimental results show that multi-exit custom instructions enhance the performance by an average of 67% compared to custom instructions limited to one basic block. A maximum speedup of 4.7, compared to a general embedded processor, and an average speedup of 1.85 was achieved on MiBench benchmark suite.

This paper presents discussion about channel fluctuation on channel estimation in digital terrestrial television broadcasting. This channel estimation uses a two-dimensional (2D) filter. In our previous work, only a structure of a lattice is considered for generation of nonrectangular 2D filter. We investigate generation of nonrectangular 2D filter with adaptive method, because we should refer to not only a lattice but also channel conditions. From the computer simulations, we show that bit error rate of the proposed filter is improved compared to that of the filter depending on only lattices.

The subject of this paper is maximum weight matchings of graphs. An edge set M of a given graph G is called a matching if and only if any pair of edges in M share no endvertices. A maximum weight matching is a matching whose total weight (total sum of edge-weights) is maximum among those of G. The maximum weight matching problem (MWM for short) is to find a maximum weight matching of a given graph. Polynomial algorithms for finding an optimum solution to MWM have already been proposed: for example, an O(|V|4) time algorithm proposed by J. Edmonds, and an O(|E||V|log |V|) time algorithm proposed by H.N. Gabow. Some applications require obtaining a matching of large total weight (not necessarily a maximum one) in realistic computing time. These existing algorithms, however, spend extremely long computing time as the size of a given graph becomes large, and several fast approximation algorithms for MWM have been proposed. In this paper, we propose six approximation algorithms GRS+, GRS_F+, GRS_R+, GRS_S+, LAM_a+ and LAM_as+. They are enhanced from known approximation ones by adding some postprocessings that consist of improved search of weight augmenting paths. Their performance is evaluated through results of computing experiment.

For the success of a large deployment of UHF RFID, easy-to-use and low-cost engineering tools to facilitate the performance evaluation are demanded particularly in installations and for trouble shooting. The measurement of interrogation area is one of the most typical industrial demands to establish the stable readability of UHF RFID. Exhaustive repetition of tag position change with a read operation and a usage of expensive measurement equipment or special interrogators are common practices to measure the interrogation area. In this paper, a practical method to measure the interrogation area of a UHF RFID by using a battery assisted passive tag (BAP) is presented. After introducing the fundamental design and performances of the BAP that we have developed, we introduce the measurement method. In the method, the target tag in the target installation is continuously traversed either manually or automatically while it is subjected to a repetitive read of a commercial interrogator. During the target tag traversal, the interrogator's commands are continuously monitored by a BAP. With an extensive analysis on interrogator commands, the BAP can differentiate between its own read timings and those of the target tag. The read timings of the target tag collected by the BAP are recorded synchronously with the target tag position, yielding a map of the interrogation area. The present method does not entail a measurement burden. It is also independent of the choice of interrogator and tag. The method is demonstrated in a practical UHF RFID installation to show that the method can measure a 40 mm resolution interrogation area measurement just by traversing the target tag at a slow walking speed, 300 mm/sec.

Ultrasonic distance measurement using the pulse-echo method is based on the determination of the time of flight of ultrasonic waves. The pulse-compression technique, in which the cross-correlation function of a detected ultrasonic wave and a transmitted ultrasonic wave is obtained, is the conventional method used for improving the resolution of distance measurement. However, the calculation of a cross-correlation operation requires high-cost digital signal processing. This paper presents a new method of sensor signal processing within the pulse-compression technique using a delta-sigma modulated single-bit digital signal. The proposed sensor signal processing method consists of a cross-correlation operation employing single-bit signal processing and a smoothing operation involving a moving average filter. The proposed method reduces the calculation cost of the digital signal processing of the pulse-compression technique.

One hardware efficient and high speed architecture for variable block size motion estimation (VBSME) in H.264 is presented in this paper. By improving the pipeline structure and processing element (PE) circuits, the system latency and hardware cost is reduced, which makes this structure more hardware efficient than the original Propagate Partial SAD architecture. For small and middle frame size picture's coding, the proposed structure can save 12.1% hardware cost compared with original Propagate Partial SAD structure. In the case of HDTV, since small inter modes trivially contribute to the coding quality, we remove modes below 88 in our design. By adopting mode reduction technique, when the set number of PE array is less than 8, the proposed mode reduction based Propagate Partial SAD structure can work at faster clock speed and consume less hardware cost than widely used SAD Tree architecture. It is more robust to the high speed timing constraint when parallel processing is considered. With TSMC 0.18 µm technology in worst work conditions (1.62 V, 125), its peak throughput of 8-set PE array structure is 720p@30 Hz with 12864 search range and 5 reference frames. 12 k gates hardware cost can be reduced by our design compared with the parallel SAD Tree architecture.

Despite the extensive literature on current conveyor-based universal (namely, low-pass, band-pass, high-pass, notch, and all-pass) biquads with three inputs and one output, no filter circuits have been reported to date which simultaneously achieve the following seven important features: (i) employment of only two current conveyors, (ii) employment of only grounded capacitors, (iii) employment of only grounded resistors, (iv) high-input and low-output impedance, (v) no need to employ inverting type input signals, (vi) no need to impose component choice conditions to realize specific filtering functions, and (vii) low active and passive sensitivity performances. This letter describes a new voltage-mode biquad circuit that satisfies all the above features simultaneously, and without trade-offs.

This paper presents a Multiprocessor System-on-Chips (MPSoC) architecture used as an execution platform for the new C-language based MPSoC design framework we are currently developing. The MPSoC architecture is based on an existing SoC platform with a commercial RISC core acting as the host CPU. We extend the existing SoC with a multiprocessor-array block that is used as the main engine to run parallel applications modeled in our design framework. Utilizing several optimizations provided by our compiler, an efficient inter-communication between processing elements with minimum overhead is implemented. A host-interface is designed to integrate the existing RISC core to the multiprocessor-array. The experimental results show that an efficacious integration is achieved, proving that the designed communication module can be used to efficiently incorporate off-the-shelf processors as a processing element for MPSoC architectures designed using our framework.

We developed test data compression scheme for scan-based BIST, aiming to compress test stimuli and responses by more than 100 times. As scan-BIST architecture, we adopt BIST-Aided Scan Test (BAST), and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 100x compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

In this paper, a fast mode decision method for intra-prediction is proposed to reduce the computational complexity of H.264/AVC encoders. With edge information, we propose a novel fast estimation algorithm to reduce the computation overhead of H.264/AVC for mode selection, where the edge direction of each coding block is detected from only part of the transformed coefficients. Hence, the computation complexity is greatly reduced. Experimental results show that the proposed fast mode decision method can eliminate about 81.34% encoding time for all intra-frame sequences with acceptable degradation of averaged PSNR and bitrates.

We report on suppressing adjacent-frequency interference (AFI) by using a RF receive bandpass-filter (BPF) with high-selectivity. By considering a high temperature superconducting (HTS) multi-pole BPF as a high selective BPF, the effect was estimated by numerical simulations. The simulations of the RF signals with an OFDM modulation transmitted to the demodulator via the BPF were carried out using the HTS BPF for 5 GHz band. The results confirmed the improvement of the bit error rate (BER) characteristic with the assumed HTS BPF with the high multi-poles under a strong AFI.

Delay jitter degrades the quality of delay-sensitive live media streaming. We investigate the use of multipath transmission with two paths to reduce delay jitter and, in this paper, propose a nearly equal delay path set configuration (NEED-PC) scheme that further improves the performance of the multipath delay jitter reduction method for delay-sensitive live media streaming. The NEED-PC scheme configures a pair of a maximally node-disjoint paths that have nearly equal path delays and satisfy a given delay constraint. The results of our simulation experiments show that path sets configured by the NEED-PC scheme exhibit better delay jitter reduction characteristics than a conventional scheme that chooses the shortest path as the primary path. We evaluate the performance of path sets configured by the NEED-PC scheme and find that the NEED-PC scheme reduces delay jitter when it is applied to a multipath delay jitter reduction method. We also investigate the trade-off between reduced delay jitter and the increased traffic load incurred by applying multipath transmission to more flows. The results show that the NEED-PC scheme is practically effective even if the amount of additional redundant traffic caused by using multipath transmission is taken into account.

Image segmentation is an essential processing step for many image analysis applications. In this paper, a novel image segmentation algorithm using fuzzy C-means clustering (FCM) with spatial constraints based on Markov random field (MRF) via Bayesian theory is proposed. Due to disregard of spatial constraint information, the FCM algorithm fails to segment images corrupted by noise. In order to improve the robustness of FCM to noise, a powerful model for the membership functions that incorporates local correlation is given by MRF defined through a Gibbs function. Then spatial information is incorporated into the FCM by Bayesian theory. Therefore, the proposed algorithm has both the advantages of the FCM and MRF, and is robust to noise. Experimental results on the synthetic and real-world images are given to demonstrate the robustness and validity of the proposed algorithm.

Realistic representations using extremely high quality images are becoming increasingly popular. For example, digital cinemas can now display moving pictures composed of high-resolution digital images. Although these applications focus on increasing the spatial resolution only, higher frame-rates are being considered to achieve more realistic representations. Since increasing the frame-rate increases the total amount of information, efficient coding methods are required. However, its statistical properties are not clarified. This paper establishes for high frame-rate video a mathematical model of the relationship between frame-rate and bit-rate. A coding experiment confirms the validity of the mathematical model.

We developed a 44 SFQ network switch prototype system and demonstrated its operation at 10 Gbps. The system's core is composed of two SFQ chips: a 44 switch and a 6-channel voltage driver. The 44 switch chip contained both a switch fabric (i.e. a data path) and a switch scheduler (i.e. a controller). Both chips were attached to a multi-chip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm5-mm die. An NEC standard 2.5-kA/cm2 fabrication process was used for the switch chip. We increased the critical current density to 10 kA/cm2 for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4 K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10 Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40 GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10 Gbps and found that it was on the order of 10-13 for the 44 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5 mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.

We have developed the fabrication process, the circuit design technology, and the cryopackaging technology for high-Tc single flux quantum (SFQ) devices with the aim of application to an analog-to-digital (A/D) converter circuit for future wireless communication and a sampler system for high-speed measurements. Reproducibility of fabricating ramp-edge Josephson junctions with IcRn products above 1 mV at 40 K and small Ic spreads on a superconducting groundplane was much improved by employing smooth multilayer structures and optimizing the junction fabrication process. The separated base-electrode layout (SBL) method that suppresses the Jc spread for interface-modified junctions in circuits was developed. This method enabled low-frequency logic operations of various elementary SFQ circuits with relatively wide bias current margins and operation of a toggle-flip-flop (T-FF) above 200 GHz at 40 K. Operation of a 1:2 demultiplexer, one of main elements of a hybrid-type Σ-Δ A/D converter circuit, was also demonstrated. We developed a sampler system in which a sampler circuit with a potential bandwidth over 100 GHz was cooled by a compact stirling cooler, and waveform observation experiments confirmed the actual system bandwidth well over 50 GHz.

We propose a noise suppression algorithm with the Kalman filter theory. The algorithm aims to achieve robust noise suppression for the additive white and colored disturbance from the canonical state space models with (i) a state equation composed of the speech signal and (ii) an observation equation composed of the speech signal and additive noise. The remarkable features of the proposed algorithm are (1) applied to adaptive white and colored noises where the additive colored noise uses babble noise, (2) realization of high performance noise suppression without sacrificing high quality of the speech signal despite simple noise suppression using only the Kalman filter algorithm, while many conventional methods based on the Kalman filter theory usually perform the noise suppression using the parameter estimation algorithm of AR (auto-regressive) system and the Kalman filter algorithm. We show the effectiveness of the proposed method, which utilizes the Kalman filter theory for the proposed canonical state space model with the colored driving source, using numerical results and subjective evaluation results.

This paper proposes a novel technique in designing the optimum pulse shape for ultra wideband (UWB) systems under the presence of timing jitter. In the UWB systems, pulse transmission power and timing jitter tolerance are crucial keys to communications success. While there is a strong desire to maximize both of them, one must be traded off against the other. In the literature, much effort has been devoted to separately optimize each of them without considering the drawback to the other. In this paper, both factors are jointly considered. The proposed pulse attains the adequate power to survive the noise floor and at the same time provides good resistance to the timing jitter. The proposed pulse also meets the power spectral mask restriction as prescribed by the Federal Communications Commission (FCC) for indoor UWB systems. Simulation results confirm the advantages of the proposed pulse over other previously known UWB pulses. Parameters of the proposed optimization algorithm are also investigated in this paper.

This paper includes different approaches for analysis of a thin-wire antenna in the presence of de-ionized water box at different temperatures as a high-permittivity three-dimensional dielectric body. In continuation with the previous work of authors, first, the coupled tensor-volume/line integral equations is solved by using Galerkin-based moment method (MoM) consisting of a combination of entire-domain and sub-domain basis functions including three-dimensional polynomials with different degrees. Then, the accuracy of such MoM, specifically for a high-permittivity dielectric scatterer, is substantiated by comparing its numerical results with that of FDTD method and some experimental data.