In Distributed detection systems, restricting the output of the local decision to one bit certainly implies a substantial information loss. In this paper, we consider the fuzzy detection, which uses a function called membership function for mapping the observation space of each local detector to a value between 0 and 1, indicating the degree of assurance about presence or absence of a signal. In this case, we examine the problem of distributed Maximum Likelihood (ML) and Order Statistic (OS) constant false alarm rate (CFAR) detections using fuzzy fusion rules such as "Algebraic Product"(AP), "Algebraic Sum"(AS), "Union"(Un) and "Intersection"(IS) in the fusion centre. For the Weibull clutter, the expression of the membership function based on the ML or OS CFAR processors in the local detectors is also obtained. For comparison, we consider a binary distributed detector, which uses the Maximum Likelihood and Algebraic Product (MLAP) or Order Statistic and Algebraic Product (OSAP) CFAR processors as the local detectors. In homogenous and non homogenous situations, multiple targets or clutter edge, the performances of the fuzzy and binary distributed detectors are analyzed and compared. The simulation results indicate the superior and robust performance of the distributed systems using fuzzy detection in the homogenous and non homogenous situations.

This paper reviews recent world-wide progress in silicon-based photonics-and-optoelectronics in order to provide a context for the papers in this special section of the IEICE Transactions. The impact of present and potential applications is discussed.

This paper presents a methodology for performing on-line voltage risk identification (VRI) in power supply networks using hyperrectangular composite neural networks (HRCNNs) and synchronized phasor measurements. The FHRCNN presented in this study integrates the paradigm of neural networks with the concept of knowledge-based approaches, rendering them both more useful than when applied alone. The fuzzy rules extracted from the dynamic data relating to the power system formalize the knowledge applied by experts when conducting the voltage risk assessment procedure. The efficiency of the proposed technique is demonstrated via its application to the Taiwan Power Provider System (Tai-Power System) under various operating conditions. Overall, the results indicated that the proposed scheme achieves a minimum 97 % success rate in determining the current voltage security level.

Burn-in is a widely used method to improve the quality of products or systems after they have been produced. In this paper, optimal burn-in procedures for a system with two types of failures (i.e., minor and catastrophic failures) are investigated. A new system surviving burn-in time b is put into field operation and the system is used under a warranty policy under which the manufacturer agrees to provide a replacement system for any system that fails to achieve a lifetime of at least w. Upper bounds for optimal burn-in time minimizing the total expected warranty cost are obtained under a more general assumption on the shape of the failure rate function which includes the bathtub shaped failure rate function as a special case.

A multi-path structure is proposed for reduction in effect of digital substrate noise which degrades analog circuit performance. As an example low-pass filters are implemented in a 0.18-µm CMOS process. 11-dBm reduction in digital substrate noise is achieved as compared with a conventional structure.

As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the most effective methods is based on clock gating to shut off the clock when the modules are idle. However, previous works on gated clock tree power minimization are mostly focused on clock routing and the improvements are often limited by the given registers placement. The purpose of this work is to navigate the registers during placement to further reduce the clock tree power based on clock gating. Our method performs activity-aware register clustering that reduces the clock tree power not only by clumping the registers into a smaller area, but also by pulling the registers with the similar activity patterns closely to shut off the clock more time for the resultant subtrees. In order to reduce the impact of signal nets wirelength and power due to register clustering, we apply the timing and activity based net weighting in [14], which reduces the nets switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. To tradeoff the power dissipated by the clock tree and the control signal, we extend the idea of local ungating in [6] and propose an algorithm of gate control signal optimization, which still sets the gate enable signal high if a register is active for a number of consecutive clock cycles. Experimental results on a set of MCNC benchmarks show that our approach is able to reduce the power and total wirelength of clock tree greatly with minimal overheads.

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an auto-switching encoder for efficient digital processing is also presented. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5 mW of power. The measured result of figure-of-merit (FoM) is 0.93 [pJ/convstep]. The active chip occupies an area of 0.28 mm2 in 0.18 µm CMOS technology.

Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). In this letter, a low-power low-noise clock signal generator for ADCs is described. As a clock signal generator, a ring-VCO-based charge pump PLL is used to reduce power dissipation within a given jitter specification. The clock signal generator is fabricated on a CMOS chip with 200-MSPS 10-bit ADC. The measured results show that the ADC keeps a 60-MHz input bandwidth and 53-dB dynamic range and a next-generation mobile wireless terminal can be realized with the ADCs and the on-chip low-power clock generator.

In this review paper we showcase recent activities on silicon photonics science and technology research in Hong Kong regarding two important topical areas--microresonator devices and optical nonlinearities. Our work on silicon microresonator filters, switches and modulators have shown promise for the nascent development of on-chip optoelectronic signal processing systems, while our studies on optical nonlinearities have contributed to basic understanding of silicon-based optically-pumped light sources and helium-implanted detectors. Here, we review our various passive and electro-optic active microresonator devices including (i) cascaded microring resonator cross-connect filters, (ii) NRZ-to-PRZ data format converters using a microring resonator notch filter, (iii) GHz-speed carrier-injection-based microring resonator modulators and 0.5-GHz-speed carrier-injection-based microdisk resonator modulators, and (iv) electrically reconfigurable microring resonator add-drop filters and electro-optic logic switches using interferometric resonance control. On the nonlinear waveguide front, we review the main nonlinear optical effects in silicon, and show that even at fairly modest average powers two-photon absorption and the accompanied free-carrier linear absorption could lead to optical limiting and a dramatic reduction in the effective lengths of nonlinear devices.

The average bit error rate performances of M-ary orthogonal code shift keying (CSK) in Rician fading environments are analyzed in this letter. CSK is a digital modulation scheme that uses a code set as M-ary signals. In CSK, one code is selected from a code set containing M codes according to the information data. A signal is modulated by using this code and the effect of fading can be reduced by applying interleaving to the elements of the codes. In the analysis, the bit error probability is derived in closed form expression by using the Chernoff bound. The analysis results show that the error probability decreases when the code length is increased and that an arbitrarily small error probability is achieved as the code length approaches infinity, provided that Eb/N0 exceeds 1.42 dB.

This paper addresses the problem of maximizing the protocol capacity of 802.11e networks, under the assumption that each access category (AC) has the same packet length. We prove that the maximal protocol capacity can be achieved at an optimal operating point with the medium idle probability of , where Tc* is the duration of collision time in terms of slot unit. Our results indicate that the optimal operating point is independent of the number of stations and throughput ratio among ACs, which means the proposed analytical results still hold even when throughput ratio and station number are time-varying. Further, we show that the maximal protocol capacity can be achieved in saturated cases by properly choosing the protocol parameters. We present a parameter configuration algorithm to achieve both efficient channel utilization and proportional fairness in IEEE 802.11e EDCA networks. Extensive simulation and analytical results are presented to verify the proposed ideas.

Real-time content analysis is typically a bottleneck in Web filtering. To accelerate the filtering process, this work presents a simple, but effective early decision algorithm that analyzes only part of the Web content. This algorithm can make the filtering decision, either to block or to pass the Web content, as soon as it is confident with a high probability that the content really belongs to a banned or an allowed category. Experiments show the algorithm needs to examine only around one-fourth of the Web content on average, while the accuracy remains fairly good: 89% for the banned content and 93% for the allowed content. This algorithm can complement other Web filtering approaches, such as URL blocking, to filter the Web content with high accuracy and efficiency. Text classification algorithms in other applications can also follow the principle of early decision to accelerate their applications.

The research on displacement vector detection has gained increasing attention in recent years. However, no relationship between displacement vectors and the outlines of objects in motion has been established. We describe a new method of detecting displacement vectors through edge segment detection by emphasizing the correlation between displacement vectors and their outlines. Specifically, after detecting an edge segment, the direction of motion of the edge segment can be inferred through the variation in the values of the Laplacian-Gaussian filter at the position near the edge segment before and after the motion. Then, by observing the degrees of displacement before and after the motion, the displacement vector can be calculated. The accuracy compared to other methods of displacement vector detection demonstrates the feasibility of this method.

In this letter, a computational approach for solving cross-coupled algebraic Riccati equations (CAREs) is investigated. The main purpose of this letter is to propose a new algorithm that combines Newton's method with a gradient-based iterative (GI) algorithm for solving CAREs. In particular, it is noteworthy that both a quadratic convergence under an appropriate initial condition and reduction in dimensions for matrix computation are both achieved. A numerical example is provided to demonstrate the efficiency of this proposed algorithm.

A new Hybrid-Carry-Selection (HCS) approach for deriving an efficient modulo 2n-1 addition is presented in this study. Its resulting adder architecture is simple and applicable for all n values. Based on 180-nm CMOS technology, the HCS-based modulo 2n-1 adder demonstrates its superiority in Area-Time (AT) performance over existing solutions.

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.

Meeting the tough linearity and noise required by GSM and UMTS receivers in CMOS technology is challenging. A new IIP2 calibration technique based on canceling the second order nonlinearities of mixer, generated in the input RF transistors, is introduced. By using this technique about 22 dB mixer IIP2 improvement is achieved. The proposed calibration circuit can be used in multi-standard mixer because of high bandwidth of the calibration circuitry. Moreover it can work with voltage supplies as low as 1 V. Using this technique a multi-standard mixer supporting PCS, UMTS and IEEE802.11b-g is developed. The design is done in CMOS 65 nm technology with 1.2 V supply while it consumes about 7 mA current.

This paper addresses the on-resistance (Ron) extraction of the DMOS based driver in Power IC designs. The proposed method can extract Ron of a driver from its layout data for the arbitrarily shaped metallization patterns. Such a driver is usually composed of arbitrarily shaped metals, arrayed vias, and DMOS transistors. We use FEM to extract the parasitic resistance of the source/drain metals since its strong contribution to Ron. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. For a layout in which the DMOS cells are regularly placed, a sub-domain reuse procedure is also proposed, which obtained a dramatic speedup for the extraction. Even without the sub-domain reuse, our method still shows advantage in runtime and memory usage according to the simulation results.

In this paper, we study a problem of inferring blood relationships which satisfy a given matrix of genetic distances between all pairs of n nodes. Blood relationships are represented by our proposed graph class, which is called a pedigree graph. A pedigree graph is a directed acyclic graph in which the maximum indegree is at most two. We show that the number of pedigree graphs which satisfy the condition of given genetic distances may be exponential, but they can be represented by one directed acyclic graph with n nodes. Moreover, an O(n3) time algorithm which solves the problem is also given. Although phylogenetic trees and phylogenetic networks are similar data structures to pedigree graphs, it seems that inferring methods for phylogenetic trees and networks cannot be applied to infer pedigree graphs since nodes of phylogenetic trees and networks represent species whereas nodes of pedigree graphs represent individuals. We also show an O(n2) time algorithm which detects a contradiction between a given pedigree graph and distance matrix of genetic distances.