Nowadays IEEE 802.11 wireless local area networks (WLANs) support multiple transmission rates. To achieve the best performance, transmitting stations adopt the various forms of automatic rate fallback (ARF). However, ARF suffers from severe performance degradation as the number of transmitting stations increases. In this paper, we propose a new rate adaptation scheme which adjusts the ARF's up/down threshold according to the channel contention level. Simulation result shows that the proposed scheme achieves fairly good performance compared with the existing schemes.

The paper presents a novel approach to estimate the performance of MPI collective communications. Our objective is to help researchers to make appropriate decisions on their message-passing applications. For each collective communication, we attempt to apply LogGP and P-LogP standard point-to-point models. The resulted models are compared with the empirical data in order to identify the most suitable for performance characterization of collective operations. For the communications on large clusters with large size messages, the network contention problem can significantly affect the performance. Hence, to reduce the relative gap between the prediction and the measured runtime, the contention issue is also modeled, by a queuing theory analysis method, and taken in account with the total performance estimation. The experiments performed on a cluster which consists of 64 processors interconnected by Gigabit Ethernet network show encouraging results. For any collective operation, given a number of processors and a range of message sizes, there is at least one model that predicts the performance precisely. We could achieve a gap between the predicted and the measured run-time around 15%. Thus, by handling the contention problem, we could reduce around 80% of the relative gap.

We propose the construction of an appearance manifold with embedded view-dependent covariance matrix to recognize 3D objects which are influenced by geometric distortions and quality degradation effects. The appearance manifold is used to capture the pose variability, while the covariance matrix is used to learn the distribution of samples for gaining noise-invariance. However, since the appearance of an object in the captured image is different for every different pose, the covariance matrix value is also different for every pose position. Therefore, it is important to embed view-dependent covariance matrices in the manifold of an object. We propose two models of constructing an appearance manifold with view-dependent covariance matrix, called the View-dependent Covariance matrix by training-Point Interpolation (VCPI) and View-dependent Covariance matrix by Eigenvector Interpolation (VCEI) methods. Here, the embedded view-dependent covariance matrix of the VCPI method is obtained by interpolating every training-points from one pose to other training-points in a consecutive pose. Meanwhile, in the VCEI method, the embedded view-dependent covariance matrix is obtained by interpolating only the eigenvectors and eigenvalues without considering the correspondences of each training image. As it embeds the covariance matrix in manifold, our view-dependent covariance matrix methods are robust to any pose changes and are also noise invariant. Our main goal is to construct a robust and efficient manifold with embedded view-dependent covariance matrix for recognizing objects from images which are influenced with various degradation effects.

Bubble-sort graphs are variants of Cayley graphs. A bubble-sort graph is suitable as a topology for massively parallel systems because of its simple and regular structure. Therefore, in this study, we focus on n-bubble-sort graphs and propose an algorithm to obtain n-1 disjoint paths between two arbitrary nodes in time bounded by a polynomial in n, the degree of the graph plus one. We estimate the time complexity of the algorithm and the sum of the path lengths after proving the correctness of the algorithm. In addition, we report the results of computer experiments evaluating the average performance of the algorithm.

This paper presents a new low power BIST TPG scheme for reducing scan transitions. It uses a transition freezing and melting method which is implemented of the transition freezing block and a MUX. When random test patterns are generated from an LFSR, transitions of those patterns satisfy pseudo-random Gaussian distribution. The proposed technique freezes transitions of patterns using a freezing value. Experimental results show that the proposed BIST TPG schemes can reduce average power reduction by about 60% without performance loss and peak power by about 30% in ISCAS'89 benchmark circuits.

This work presents an FFT/IFFT core compiler particularly suited for the VLSI implementation of OFDM communication systems. The tool employs an architecture template based on the pipelined cascade principle. The generated cores support run-time programmable length and transform type selection, enabling seamless integration into multiple mode and multiple standard terminals. A distinctive feature of the tool is its accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results of the generated macrocells are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. When compared with other tools for automatic FFT core generation, the proposed environment produces macrocells with lower circuit complexity expressed as gate count and RAM/ROM bits, while keeping the same system level performance in terms of throughput, transform size and numerical accuracy.

This paper deals with a TM plane wave reflection and transmission from a one-dimensional random slab with stratified fluctuation by means of the stochastic functional approach. Based on a previous manner [IEICE Trans. Electron. E88-C, 4, pp.713-720, 2005], an explicit form of the random wavefield is obtained in terms of a Wiener-Hermite expansion with approximate expansion coefficients (Wiener kernels) under small fluctuation. The optical theorem and coherent reflection coefficient are illustrated in figures for several physical parameters. It is then found that the optical theorem by use of the first two or three order Wiener kernels holds with good accuracy and a shift of Brewster's angle appears in the coherent reflection.

Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

In this paper, we propose and analyze the adaptive modulation system with optimal Turbo Coded V-BLAST (Vertical-Bell-lab Layered Space-Time) technique that adopts extrinsic information from a MAP (Maximum A Posteriori) decoder with iterative decoding as a priori probability in two decoding procedures of V-BLAST scheme; the ordering and the slicing. Also, we consider the AMC (Adaptive Modulation and Coding) using the conventional Turbo Coded V-BLAST technique that simply combines the V-BLAST scheme with the turbo coding scheme. And we compare the proposed iterative decoding algorithm to a conventional V-BLAST decoding algorithm and a ML (Maximum Likelihood) decoding algorithm. In this analysis, the MIMO (Multiple Input Multiple Output) and the STD (Selection Transmit Diversity) schemes are assumed to be parts of the system for performance improvement. Results indicate that the proposed systems achieve better throughput performance than the conventional systems over the whole SNR (Signal to Noise Ratio) range. In terms of transmission rate performance, the suggested system is close in proximity to the conventional system using the ML decoding algorithm. In addition, the simulation result shows that the maximum throughput improvement in each MIMO scheme is respectively about 350 kbps, 460 kbps, and 740 kbps. It is suggested that the effect of the proposed iterative decoding algorithm accordingly gets higher as the number of system antenna increases.

During software requirements analysis, developers and stakeholders have many alternatives of requirements to be achieved and should make decisions to select an alternative out of them. There are two significant points to be considered for supporting these decision making processes in requirements analysis; 1) dependencies among alternatives and 2) evaluation based on multi-criteria and their trade-off. This paper proposes the technique to address the above two issues by using an extended version of goal-oriented analysis. In goal-oriented analysis, elicited goals and their dependencies are represented with an AND-OR acyclic directed graph. We use this technique to model the dependencies of the alternatives. Furthermore we associate attribute values and their propagation rules with nodes and edges in a goal graph in order to evaluate the alternatives with them. The attributes and their calculation rules greatly depend on the characteristics of a development project. Thus, in our approach, we select and use the attributes and their rules that can be appropriate for the project. TOPSIS method is adopted to show alternatives and their resulting attribute values.

One of the approaches to improve program understanding is to extract what kinds of design pattern are used in existing object-oriented software. This paper proposes a technique for efficiently and accurately detecting occurrences of design patterns included in source codes. We use both static and dynamic analyses to achieve the detection with high accuracy. Moreover, to reduce computation and maintenance costs, detection conditions are hierarchically specified based on Pree's meta patterns as common structures of design patterns. The usage of Prolog to represent the detection conditions enables us to easily add and modify them. Finally, we have implemented an automated tool as an Eclipse plug-in and conducted experiments with Java programs. The experimental results show the effectiveness of our approach.

For the success of a large deployment of UHF RFID, easy-to-use and low-cost engineering tools to facilitate the performance evaluation are demanded particularly in installations and for trouble shooting. The measurement of interrogation area is one of the most typical industrial demands to establish the stable readability of UHF RFID. Exhaustive repetition of tag position change with a read operation and a usage of expensive measurement equipment or special interrogators are common practices to measure the interrogation area. In this paper, a practical method to measure the interrogation area of a UHF RFID by using a battery assisted passive tag (BAP) is presented. After introducing the fundamental design and performances of the BAP that we have developed, we introduce the measurement method. In the method, the target tag in the target installation is continuously traversed either manually or automatically while it is subjected to a repetitive read of a commercial interrogator. During the target tag traversal, the interrogator's commands are continuously monitored by a BAP. With an extensive analysis on interrogator commands, the BAP can differentiate between its own read timings and those of the target tag. The read timings of the target tag collected by the BAP are recorded synchronously with the target tag position, yielding a map of the interrogation area. The present method does not entail a measurement burden. It is also independent of the choice of interrogator and tag. The method is demonstrated in a practical UHF RFID installation to show that the method can measure a 40 mm resolution interrogation area measurement just by traversing the target tag at a slow walking speed, 300 mm/sec.

Ultrasonic distance measurement using the pulse-echo method is based on the determination of the time of flight of ultrasonic waves. The pulse-compression technique, in which the cross-correlation function of a detected ultrasonic wave and a transmitted ultrasonic wave is obtained, is the conventional method used for improving the resolution of distance measurement. However, the calculation of a cross-correlation operation requires high-cost digital signal processing. This paper presents a new method of sensor signal processing within the pulse-compression technique using a delta-sigma modulated single-bit digital signal. The proposed sensor signal processing method consists of a cross-correlation operation employing single-bit signal processing and a smoothing operation involving a moving average filter. The proposed method reduces the calculation cost of the digital signal processing of the pulse-compression technique.

In this letter, the influence of the downlink average ratio of the other cell interference to other-user interference in the serving cell (DARI) on the distributed repeater system (DRS) performance is analyzed. It is found that the improvement of DARI depends on a propagation path loss environment. Applying the computed DARI to a 3-RS DRS cell, as high as 13.9% capacity enhancement was obtained when the path loss exponent is 4.5. In addition, by using the power allocation equation, it is expected that a hexagonal DRS cell without coverage holes or excessive coverage overlap can be realized.

Video surveillance systems have a huge market, as indicated by the number of installed cameras, particularly for low-power systems. In this paper, we propose a low-power quadtree video encoder for video surveillance systems. It features a low-complexity motion estimation algorithm, an application-specific ME-MC processor, a dedicated quadtree encoder engine and a processor control-based clock-gating technique. A chip capable of encoding 30 fps VGA (640480) at 80 MHz is fabricated using 0.18 µm CMOS technology. A total of 153 K gates with 558 kbits SRAM have been integrated into a 5.0 mm3.5 mm die. The power consumption is 40.87 mW at 80 MHz for VGA at 30 fps and 1.97 mW at 3.3 MHz for QCIF at 15 fps.

This letter proposes an efficient transmit power allocation using partial channel information feedback for the closed-loop sorted QR decomposition (SQRD) based V-BLAST systems. For the feedback information, the positive real-valued diagonal elements of R are forwarded to the transmitter. With the proposed transmit power allocation that is numerically derived by the Lagrange optimization method, the bit error rate performance of the system can be remarkably improved compare to the conventional open-loop SQRD based V-BLAST systems without increasing the receiver complexity.

Utilization of electromagnetic absorbers under high power is increasing. The absorbers are used in anechoic chambers for performance estimation of high power radars. Variation of the absorption characteristics of the absorbers under such conditions is expected, due to the generation of heat or temperature change. In this paper, first the temperature distribution of a λ/4 type EM-wave absorber under high power injection is examined using the coupled method. The coupled method can calculate the electromagnetic field and all of the heat transmissions (heat transport, heat transfer and heat radiation). Next, the power injection experiment is examined using the absorber and high power instruments to get the temperature distribution experimentally. Finally the calculated and measured temperature distributions of the absorber are compared and discussed.

One hardware efficient and high speed architecture for variable block size motion estimation (VBSME) in H.264 is presented in this paper. By improving the pipeline structure and processing element (PE) circuits, the system latency and hardware cost is reduced, which makes this structure more hardware efficient than the original Propagate Partial SAD architecture. For small and middle frame size picture's coding, the proposed structure can save 12.1% hardware cost compared with original Propagate Partial SAD structure. In the case of HDTV, since small inter modes trivially contribute to the coding quality, we remove modes below 88 in our design. By adopting mode reduction technique, when the set number of PE array is less than 8, the proposed mode reduction based Propagate Partial SAD structure can work at faster clock speed and consume less hardware cost than widely used SAD Tree architecture. It is more robust to the high speed timing constraint when parallel processing is considered. With TSMC 0.18 µm technology in worst work conditions (1.62 V, 125), its peak throughput of 8-set PE array structure is 720p@30 Hz with 12864 search range and 5 reference frames. 12 k gates hardware cost can be reduced by our design compared with the parallel SAD Tree architecture.

We have developed a visual entertainment system called "Future Cast" which enables anyone to easily participate in a pre-recorded or pre-created film as an instant CG movie star. This system provides audiences with the amazing opportunity to join the cast of a movie in real-time. The Future Cast System can automatically perform all the processes required to make this possible, from capturing participants' facial characteristics to rendering them into the movie. Our system can also be applied to any movie created using the same production process. We conducted our first experimental trial demonstration of the Future Cast System at the Mitsui-Toshiba pavilion at the 2005 World Exposition in Aichi Japan.

Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for 40% or more of the total energy consumed in these systems. Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems continues to grow. Moreover, temperature is another factor that exponentially increases the leakage current. In this paper, we show the effect of temperature on the optimal (minimum-energy-consuming) cache configuration for low energy embedded systems. Our results show that for a given application and technology, the optimal cache size moves toward smaller caches at higher temperatures, due to the larger leakage. Consequently, a Temperature-Aware Configurable Cache (TACC) is an effective way to save energy in finer technologies when the embedded system is used in different temperatures. Our results show that using a TACC, up to 61% energy can be saved for instruction cache and 77% for data cache compared to a configurable cache that has been configured for only the corner-case temperature (100). Furthermore, the TACC also enhances the performance by up to 28% for the instruction cache and up to 17% for the data cache.