A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40 GHz, and the demonstration of a 47-Gbps SFQ 22 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4 K with a two-stage 1-W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (~10 Gbps/ch) and SFQ circuits (>40 GHz). An SFQ 22 switch chip, in which the MUX/DEMUX and an SFQ 22 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10 kA/cm2. An SFQ 22 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with φ 50-µm InSn solder bumps. An SFQ 22 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47 Gbps for the first time.

We propose a desk-side supercomputer with large-scale reconfigurable data-paths (LSRDPs) using superconducting rapid single-flux-quantum (RSFQ) circuits. It has several sets of computing unit which consists of a general-purpose microprocessor, an LSRDP and a memory. An LSRDP consists of a lot of, e.g., a few thousand, floating-point units (FPUs) and operand routing networks (ORNs) which connect the FPUs. We reconfigure the LSRDP to fit a computation, i.e., a group of floating-point operations, which appears in a 'for' loop of numerical programs by setting the route in ORNs before the execution of the loop. We propose to implement the LSRDPs by RSFQ circuits. The processors and the memories can be implemented by semiconductor technology. We expect that a 10 TFLOPS supercomputer, as well as a refrigerating engine, will be housed in a desk-side rack, using a near-future RSFQ process technology, such as 0.35 µm process.

A sound localization method in the proximal region is proposed, which is based on a low-cost 3D sound localization algorithm with the use of head-related transfer functions (HRTFs). The auditory parallax model is applied to the current algorithm so that more accurate HRTFs can be used for sound localization in the proximal region. In addition, head-shadowing effects based on rigid-sphere model are reproduced in the proximal region by means of a second-order IIR filter. A subjective listening test demonstrates the effectiveness of the proposed method. Embedded system implementation of the proposed method is also described claiming that the proposed method improves sound effects in the proximal region only with 5.1% increase of memory capacity and 8.3% of computational costs.

In this paper, we propose a recursive filtering algorithm to restore monochromatic images which are corrupted by general dependent additive noise. It is assumed that the equation which describes the image field is not available and a filtering algorithm is obtained using the information provided by the covariance functions of the signal, noise that affects the measurement equation, and the fourth-order moments of the signal. The proposed algorithm is obtained by an innovation approach which provides a simple derivation of the least mean-squared error linear estimators. The estimation of the grey level in each spatial coordinate is made taking into account the information provided by the grey levels located on the row of the pixel to be estimated. The proposed filtering algorithm is applied to restore images which are affected by general signal-dependent additive noise.

The letter proposes a novel subsampling-based digital image watermarking scheme resisting the permutation attack. The subsampling-based watermarking schemes have drawn great attention for their convenience and effectiveness in recent years, but the traditional subsampling-based watermarking schemes are very vulnerable to the permutation attack. In this letter, the watermark information is embedded in the average values of the 1-level DWT coefficients to resist the permutation attack. The concrete embedding process is achieved by the quantization-based method. Experimental results show that the proposed scheme can resist not only the permutation attack but also some common image processing attacks.

We developed test data compression scheme for scan-based BIST, aiming to compress test stimuli and responses by more than 100 times. As scan-BIST architecture, we adopt BIST-Aided Scan Test (BAST), and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 100x compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

This paper presents the history of superconductor digital circuits starting from several years after the discovery of the Josephson junction in 1962. The first two decades were mainly devoted to developing voltage-state logic, which is similar to semiconductor logic. Research on circuits employing the manipulation of single magnetic flux quanta resulted in a form called RSFQ in the mid-1980s; this is the basis of superconductor logic systems of today. The more difficult problem of random access memory is reviewed. We analyze the present status of the field and outline the work that lies ahead to realize a successful superconductor digital technology.

In this letter, we propose a new type of recursive least squares (RLS) algorithms without using the initial information of a parameter or a state to be estimated. The proposed RLS algorithm is first obtained for a generic linear model and is then extended to a state estimator for a stochastic state-space model. Compared with the existing algorithms, the proposed RLS algorithms are simpler and more numerically stable. It is shown through simulation that the proposed RLS algorithms have better numerical stability for digital computations than existing algorithms.

This paper proposes a novel technique in designing the optimum pulse shape for ultra wideband (UWB) systems under the presence of timing jitter. In the UWB systems, pulse transmission power and timing jitter tolerance are crucial keys to communications success. While there is a strong desire to maximize both of them, one must be traded off against the other. In the literature, much effort has been devoted to separately optimize each of them without considering the drawback to the other. In this paper, both factors are jointly considered. The proposed pulse attains the adequate power to survive the noise floor and at the same time provides good resistance to the timing jitter. The proposed pulse also meets the power spectral mask restriction as prescribed by the Federal Communications Commission (FCC) for indoor UWB systems. Simulation results confirm the advantages of the proposed pulse over other previously known UWB pulses. Parameters of the proposed optimization algorithm are also investigated in this paper.

A sweep spectrum analyzer has been improved over the years, but the fundamental method has not been changed before the 'Super Sweep' method appeared. The 'Super Sweep' method has been expected to break the limitation of the conventional sweep spectrum analyzer, a limit of the maximum sweep rate which is in inverse proportion to the square of the frequency resolution. The superior performance of the 'Super Sweep' method, however, has not been experimentally proved yet. This paper gives the experimental evaluation on the 'Super Sweep' spectrum analyzer, of which theoretical concepts have already been presented by the authors of this paper. Before giving the experimental results, we give complete analysis for a sweep spectrum analyzer and express the principle of the super-sweep operation with a complete set of equations. We developed an experimental system whose components operated in an optimum condition as the spectrum analyzer. Then we investigated its properties, a peak level reduction and broadening of the frequency resolution of the measured spectrum, by changing the sweep rate. We also confirmed that the experimental system satisfactorily detected the spectrum at least 30 times faster than the conventional method and the sweep rate was in proportion to the bandwidth of the base band signal to be analyzed. We proved that the 'Super Sweep' method broke the restriction of the sweep rate put on a conventional sweep spectrum analyzer.

Integration of light sources on a Si chip is one of milestone to establish new paradigm of LSI systems, so-called "silicon photonics." In recent years remarkable progress has been made in the Si wire waveguide technologies for optical interconnection on a Si chip. In this paper, several Er embedded materials based on silicon are surveyed from the standpoint of application to the light emission and amplification devices for silicon photonics. We have concentrated to investigate an erbium silicate (Er2SiO5) as a light source medium for silicon photonics. To mention the particular features, this material has a layered structure with 0.86-nm period and a large amount of Er (25at%) as its constituent. The single crystalline nature gives several remarkable properties for the application to silicon photonics. We also discuss our recent studies of Er2SiO5 and a possibility of the shorter waveguide amplifier.

This paper discusses the behavior of the second-order modes (Hankel singular values) of linear continuous-time systems under variable transformations with positive-real functions. That is, given a transfer function H(s) and its second-order modes, we analyze the second-order modes of transformed systems H(F(s)), where 1/F(s) is an arbitrary positive-real function. We first discuss the case of lossless positive-real transformations, and show that the second-order modes are invariant under any lossless positive-real transformation. We next consider the case of general positive-real transformations, and reveal that the values of the second-order modes are decreased under any general positive-real transformation. We achieve the derivation of these results by describing the controllability/observability Gramians of transformed systems, with the help of the lossless positive-real lemma, the positive-real lemma, and state-space formulation of transformed systems.

A rate control scheme is described for zero-forcing beamforming (ZFBF) multiuser multiple-input and multiple-output (MU-MIMO) systems with a QR-decomposition maximum likelihood detector (MLD) at the receiver. For selected users, a modulation-and-coding set is selected for each substream by estimating the per-substream post-MLD signal-to-interference-plus-noise ratio. Iterative modified QR-decomposition MLD is employed at the receiver to achieve the throughput expected from the transmitter. The simulation results demonstrated that the proposed rate-control scheme achieved the target packet error rate while increasing the throughout for ZFBF-MU-MIMO systems as the number of user candidates increases.

An important issue in the realization of optical packet-switched (OPS) networks is the resolution of packet contention caused by the lack of RAM-like optical buffering. Although an optical buffer using fiber delay lines (FDLs) has been proposed, its capacity is extremely limited. There have been several studies of this problem. One approach is deflection routing, which is widely used in electronic packet-switched networks or optical burst-switched (OBS) networks. However, in OPS networks, packet lengths are short, so that the speed requirement for route lookup is very stringent. If the network topology is geometric, such as a Manhattan Street Network (MSN), hop-by-hop routing can be implemented by simple optical logic devices without an electronic routing table. However, if the topology is not geometric, it is hard to implement deflection routing electronically or optically. Another approach is reflection routing, which is easy to implement but has a higher probability of packet loss than does deflection routing. In this paper, we propose a packet contention resolution scheme, reflection-based deflection routing, which is based on reflection routing and enables switching the reflected packet to an alternate path if its primary path remains congested. Our method alleviates the time limitation on setting an alternate path by making use of the packet reflection latency and also reduces the probability of packet loss. We evaluate the performance of the proposed method by simulation experiments and show its effectiveness.

This paper introduces an adaptive low complexity pre-processing filter to improve the coding performance of seriously degraded video sequences that is caused by the additive noise. The additive noise leads to a decrease in coding performance due to the high frequency components. By incorporating local statistics and quantization parameter into filtering process, the spurious noise is significantly attenuated and coding efficiency is improved for given quantization step size. In order to reduce the complexity of the pre-processing filter, the simplified local statistics and quantization parameter are introduced. The simulation results show the capability of the proposed algorithm.

The Earth will require sustainable electricity sources equivalent to 3 to 5 times the commercial power presently produced by 2050. Solar Power Satellite (SPS) is one option for meeting the huge future energy demand. SPS can send enormous amounts of power to the Earth as the form of microwave (MW). A highly efficient microwave power transmission (MPT) system is needed for SPS. A critical goal of SPS is to maintain highest Beam Efficiency (BE) because the microwaves from SPS will be converted to utility power unlike the MW from communication satellites. Another critical goal of SPS is to maintain Side Lobe Levels (SLL) as small as possible to reduce interference to other communication systems. One way to decrease SLL and increase BE is the edge tapering of a phased array antenna. However, tapering the excitation requires a technically complicated system. Another way of achieving minimum SLL is with randomly spaced element position but it does not guarantee higher BE and the determination of random element position is also a difficult task. Isosceles Trapezoidal Distribution (ITD) edge tapered antenna was studied for SPS as an optimization between full edge tapering and uniform amplitude distribution. The highest Beam Collection Efficiency (BCE) and lowest SLL (except maximum SLL) are possible to achieve in ITD edge tapering and ITD edge tapered antenna is technically better. The performance of ITD is further improved from the perspective of both Maximum Side Lobe Level (MSLL) and BE by using unequal spacing of the antenna elements. A remarkable reduction in MSLL is achieved with ITD edge tapering with Unequal element spacing (ITDU). BE was also highest in ITDU. Determination of unequal element position for ITDU is very easy. ITDU is a newer concept that is experimented for the first time. The merits of ITDU over ITD and Gaussian edge tapering are discussed.

This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.

A multi-path structure is proposed for reduction in effect of digital substrate noise which degrades analog circuit performance. As an example low-pass filters are implemented in a 0.18-µm CMOS process. 11-dBm reduction in digital substrate noise is achieved as compared with a conventional structure.

In this paper, we propose a novel MAC protocol with the patterned preamble technique to improve performance in terms of low power, channel utilization, and delay in wireless sensor networks. B-MAC is one of typical MAC protocols for wireless sensor networks using the duty cycle in order to achieve low-power operation. Since it works in an asynchronous fashion, B-MAC employs extended preamble and preamble sampling techniques. Even if it has outstanding performance in idle state, the overhead of these techniques is very large when packets are sent and received, because there is a lot of waste in the traditional preamble method. Instead of the simple preamble, our proposed MAC solution is to introduce more intelligent preamble with some patterns consisting of 2 phases (Tx phase & Ack phase). With this concept we implement real source code working on the mica2 platform with Tinyos-1.x version. Also, the test set-up is presented, and the test results demonstrate that the proposed protocol provides better performance in terms of delay compared to B-MAC.

A power-efficient Dickson-based charge pump circuit is proposed and verified in this paper. Using a PMOS transfer switch in the new circuit solves the problem of the output voltage loss and its body control switch can suppress the parasitic bipolar action. Comparing this new one with the conventional circuit, the new circuit generates output voltage as high as 2.9 VDD while the conventional one only 2 VDD. For their efficiency values, the new circuit has better efficiency than the conventional one by as much as 14.5% with the area overhead of 12.2% using 3.5-µm and 40-V CMOS high-voltage process.