This paper proposes two efficient rate control algorithms for Motion JPEG2000. Both methods provide accurate visual quality control under buffer constraints. Frames of the same scene usually have the similar rate-distortion (R-D) characters. The proposed methods predict the R-D models of uncoded frames forwardly or bilaterally according to those of coded frames. Experimental results demonstrate that the proposed algorithms offer visual quality improvements over similar competing methods and save a large amount of memory simultaneously.

In this paper, a coefficient-parameter embedding method into Motion-JPEG2000 (MJP2) is proposed for invertible deinterlacing with variable coefficients. Invertible deinterlacing, which the authors have developed before, can be used as a preprocess of frame-based motion picture codec, such as MJP2, for interlaced videos. When the conventional field-interleaving is used instead, comb-tooth artifacts appear around edges of moving objects. On the other hand, the invertible deinterlacing technique allows us to suppress the comb-tooth artifacts and also guaranties recovery of original pictures. As previous works, the authors have developed a variable coefficient scheme with a motion detector, which realizes adaptability to local characteristics of given pictures. However, when this deinterlacing technique is applied to a video codec, coefficient parameters have to be sent to receivers for original picture recovery. This paper proposes a parameter-embedding technique in MJP2 and constructs a standard stream which consists both of picture data and the parameters. The parameters are embedded into the LH1 component of wavelet transform domain through the ROI (region of interest) function of JPEG2000 without significant loss in the performance of comb-tooth suppression. Some experimental results show the feasibility of our proposed scheme.

Most commercial Web sites dynamically generate their contents through a three-tier server architecture composed of a Web server, an application server, and a database server. In such an architecture, the database server easily becomes a bottleneck to the overall performance. In this paper, we propose WDBAccel, a high-performance database server accelerator that significantly improves the throughput of database processing. WDBAccel eliminates costly, complex query processing needed to obtain query results by reusing the results from previous queries for subsequent queries. This differentiates WDBAccel from other database cache systems, which employ traditional query processing. WDBAccel further improves its performance by fully utilizing main memory as the primary storage. This paper presents the design and implementation of the WDBAccel as well as the results of performance evaluation with a prototype.

A new Kalman carrier synchronization algorithm is developed for high-order QAM transmission to reduce complexity compared to the conventional Kalman approach. The state model in the proposed algorithm employs only phase, instead of both phase and frequency, as in the conventional method. A reduced-observation model is also introduced to eliminate matrix operations in the Kalman recursions. Simulations results show that the one-state Kalman algorithm has better performance and lower complexity than the two-state Kalman algorithm. The cable modem downstream system is applied to demonstrate the effectiveness of the proposed algorithm.

A powerful HARQ-based linear precoding scheme is proposed to utilize the flexibility of post-combining HARQ strategy in MIMO communications systems. The scheme selects the appropriate symbols and transmit powers for each eigen-mode to acquire more performance gains. Simulation results show that the proposed scheme achieves about 5.5 dB signal-to-noise ratio gains over original spatial multiplexing scheme at an average bit error rate of 10-4. Furthermore, the gap between the two schemes increases with the number of transmissions.

This paper reports on a study of the interference effects from 2 types of ultra wideband (UWB) sources on a QPSK transmission system by simulation. The culprit UWB sources were: multi-band orthogonal frequency-division multiple-access (MB-OFDM) and direct-sequence UWB (DS-UWB), which were modeled on the proposal specifications in the IEEE 802.15.3a to standardize high-speed wireless personal area networks. Average bit error rate (BER) degradation of the victim system was evaluated under in-band interference from the UWB signals. The proposed modified equivalent baseband system was employed in the simulation in order to reduce the simulation costs. Interference effects from the UWB sources were also examined under a Rayleigh fading channel.

Recently, Dutta and Barua proposed provably secure constant round authenticated group key agreement protocols in dynamic scenario. In this letter, we show that their Leave Protocol does not provide forward secrecy, that is, a leaving user can still obtain the new session key used in subsequent sessions.

This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to describe and analyze addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with multiple-valued logic devices, while a low-level CTD represents a network of primitive components directly mapped onto binary logic devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs. This paper demonstrates the interpretation of redundant arithmetic adders based on CTDs. We first introduce an extension of CTDs to represent possible redundant arithmetic adders with limited carry propagation. Using the extended version of CTDs, we can classify the conventional adder structures including those using emerging devices into three types in a systematic way.

We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.

Data mining across different companies, organizations, online shops, or the likes is necessary so as to discover valuable shared patterns, associations, trends, or dependencies in their shared data. Privacy, however, is a concern. In many situations it is required that data mining should be conducted without any privacy being violated. In response to this requirement, in this paper we propose an effective distributed privacy-preserving data mining approach called SDDM. SDDM is characterized by its ability to resist collusion. Unless the number of colluding sites in a distributed system is larger than or equal to 4, privacy cannot be violated. Results of performance study demonstrated the effectiveness of SDDM.

Fundamental limitation on assisting a write margin (WRTM) by reducing the cell terminal bias (VDDM) has been made clear for the first time and the new cell terminal biasing scheme featuring a differential VDDM (Diff-VDDM) control has been proposed to address the issues which the conventional schemes proposed so far can not overcome [1]-[5]. Since Diff-VDDM biasing scheme can meet the both of the requirements simultaneously of 1) reducing drivability for the PMOS load transistor on the "Low" written bit-line (BL) side, and 2) increasing drivability for the other side PMOS for a write recovery, it can provide a lower minimum operating voltage (Vdd_min) for the write operation even if considering a sufficiently-large random threshold voltage (Vth) variations. The following points have been shown based on an actual 65 nm CMOS device variation data and the implemented layout data that 1) Vdd_min for the write operation can be lowered from Vdd=1.1 V down to 0.8 V when considering a 4-sigma (σ) variation, 2) the write recovery time can be reduced by 92% and 70% that for the conventional schemes [1],[2] at Vdd=0.7 V and 1.0 V, respectively, and 3) WRTM defined by the percentage (%) of the required (BL pull-down level/Vdd) to flip the cell nodes for the write operation can be relaxed by 2.6-fold and 1.4-fold that for the conventional schemes [1],[2] at Vdd=0.75 V and 1.0 V, respectively. As an actual implementation in a 65 nm CMOS, a 32-kbit single-port SRAM macro design and the measured butterfly curves have been demonstrated.

In computer simulation of a large number of moving objects (MOs), how to enlarge Δt (the interval between the simulation time steps) without introducing causality errors is one of the primary keys to enhancing performance. Causality errors can be avoided by using the same Δt among related MOs when they are in the scene of detection (SoD). But in a large-scale MO simulation, MOs interact with one another in a complicated manner requiring a large calculation cost to predict the beginning time of SoD. In this paper we propose an event-aware dynamic time step synchronization method (DTSS) for distributed MO simulation, which increases Δt without introducing causality errors and speeds up the simulation. DTSS can be implemented with little calculation cost because: (1) DTSS does not calculate the beginning time of SoD exactly, but calculates the time for possible entry into SoD with a simple mechanisim, and (2) MO simulation consists of a "movement"-phase and a "detection"-phase in which the distance-calculation between MOs requires a heavy load, and DTSS utilizes the distance values to calculate Δt. In this paper, we also discuss a suitable HLA based time management mechanism to implement DTSS on a distributed computing environment. In the performance evaluation of DTSS, the calculation cost of DTSS is implemented by using the HLA suitable time management mechanism. The results show that DTSS can be executed within the ideal time plus its 1% over-cost when a basic scenario of war-game simulation is employed. Therefore if the ratio of SoD to the total simulation is small, the execution time is expected to decrease to nearly this ratio. We also introduce the criterion for determining when DTSS is superior to the conventional method by using the performance evaluation results. The results presented in this paper are effectively utilized when DTSS is applied to practical applications.

For mobile visual communications, the development of more robust and efficient video traffic control and transmission techniques remains one of the most important issues. Foveated video originates from visual entropy reduction by removing undetectable high visual frequencies that occur at a distance from the fixation point. In this paper, compression gain is defined and measured to quantify the enhanced performance when the visual throughput of the regions of interest (ROI) is increased over a capacity-limited channel.

In this paper, a novel cost effective interconnection network for two-way pipelined SIMD-based reconfigurable computing processor is proposed. Our reconfigurable computing engine is composed of the SIMD-based function units, flexible interconnection networks, and two-bank on-chip memories. In order to connect the function units, the reconfigurable network is proposed to connect all neighbors of each function unit. The proposed interconnection network is a kind of full and bidirectional connection with the data duplication to perform the data-parallelism applications efficiently. Moreover, it is a multistage network to accomplish the high flexibility and low hardware cost.

This paper presents a semi-blind algorithm for multiuser interference cancellation and fading amplitude estimation for downlink MIMO DS-CDMA systems with multipath fading channels. Taking advantage of the space-time information of the parametric multipath channel, the proposed algorithm first uses a space-time channel decoupler to suppress multiuser interference and then decomposes the channel into a set of parallel subchannels each containing the signal of the desired user on an individual multipath. Two criteria, the complementary orthogonal projection (COP) and the minimum variance distortionless response (MVDR), are employed by the space-time decoupler to achieve interference suppression and signal separation. The fading amplitudes can then be estimated from the eigen space of the output of the space-time channel decoupler. It follows that the signal of interest can be maximally combined in a pathwise manner and then differentially decoded.

We have introduced an extremely high resolution video system 'Super Hi-Vision' at the Kyushu National Museum. This feature opened in October 2005 with the purpose of exhibiting high-quality images of national treasures and traditional arts and crafts to its visitors. The system achieves high resolution using the spatial pixel offset method, quadrupling the horizontal and vertical resolution of HDTV. To display the images with high fidelity, it is important to manipulate the images on the basis of the system characteristics. This paper reports on the efforts to ensure image quality for this Super Hi-Vision System, focusing on resolution and color reproduction.

Accurate on-chip 100-ps/100-µV waveform measurements of signal transition in a large-scale digital integrated circuit clearly demonstrates the correlation of dynamic delay variation with power supply noise waveforms. In addition to the linear dependence of delay increase with the height of static IR drop, the distortion of a signal waveform during a logic transition that is induced by dynamic power supply noise causes significant delay variation. However, an analysis reveals that average modeling of dynamic power supply noise, which is often used in conventional simulation techniques, cannot match the experimentally measured values. Our proposed circuit simulation technique, which incorporates time-domain power supply noise waveform macro models along with parasitic impedance networks, reproduces the delay variation well, even with a relative timing difference among different clock domains. Such basic knowledge can be applied in precise delay calculations that consider dynamic power supply noise, a crucial factor in deep sub-100-nm LSI design.

An enhanced Ultra Wideband (UWB) signaling scheme that employs PSWF (Prolate Spheroidal Wave Functions)-based orthogonal chip pulses and ternary complementary code sets is proposed for Direct-Sequence (DS) UWB systems. Every information bit of each user is modulated and transmitted over a set of parallel sequences of PSWF-based orthogonal chip pulses and are further assigned to a ternary complementary code set with additional zero padding if necessary. Moreover, the ternary complementary code sets are generated to be mutually orthogonal and assigned to any pair of multiple users. Hence, the mitigation of multipath interference as well as multiple user interference (MUI) can be expected. Furthermore, the ternary code length can be greatly shortened by taking advantage of pulse and code orthogonality. Thus, the proposed transmission scheme is especially suitable for high data rate DS-UWB systems that offer very high flexibility.

Carbon nanotubes (CNTs) offer unique properties such as highest current density exceeding 109 A/cm2, ultra-high thermal conductivity as high as that of diamond, ballistic transport along the tube and extremely high mechanical strength with high aspect ratio of more than 1000. Because of these remarkable properties, they have been expected for use as future wiring materials to solve several problems, for examples, stress and electro-migration, heat removal and fabrication of a small-sized via in future LSIs. In this paper, we demonstrate present status of CNT material technologies and the potential of metallic CNT vias. In particular, we report our original catalytic nano-particle technique for controlling the diameter and density of CNTs. We have succeeded in forming a 40-nm via with the CNT density of 91011/cm2, which is the highest density ever reported. The low temperature CVD growth and the electrical properties of CNT vias are also discussed.

We have developed a code-division-multiplexing (CDM) transmission scheme for future road-vehicle communication systems, which uses cyclic shifted-and-extended (CSE) codes generated from a basic code with superior auto-correlation characteristics. This paper proposes to use a Quasi-Orthogonal (QO) sequence as the basic code. Its auto-correlation values are zero except at zero and middle shifts. When the CDM transmission is performed by the CSE codes based on the QO sequence, a desired correlation value is, at a receiver, interfered by the auto-correlation value at middle shift. Therefore, an elimination technique for the interfered correlation value is proposed and realizes zero cross-correlation characteristics within the cyclical shift interval. The new CDM transmission scheme based on the proposed scheme is evaluated by computer simulations in terms of the bit-error-rate performance.