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[Keyword] TE(21534hit)

12361-12380hit(21534hit)

  • An Improvement of Communication Environment for ETC System by Using Transparent EM Wave Absorber

    Hiroshi KURIHARA  Yoshihito HIRAI  Koji TAKIZAWA  Takeo IWATA  Osamu HASHIMOTO  

     
    PAPER-Electromagnetic Theory

      Vol:
    E88-C No:12
      Page(s):
    2350-2357

    When a large-size car exists on the ETC lane (Electronic Toll Collection System), there is the possibility that the interference on the adjacent lane occurs by the scattering waves from one. In this paper, we propose a new improvement method which the transparent EM wave absorber is placed between the ETC lane and the adjacent one in order to suppress the scattering waves from a large-size car. Therefore, we design the transparent EM wave absorber which consists of the transparent resistive and conductive films. Then, this absorber is produced, and its reflection and transmission coefficients are evaluated. In addition, its transmittance in optics is evaluated. As the results, the reflectivity of this absorber is obtained lower than -20 dB in the oblique incident angle from 0to 30at 5.8 GHz circular polarized wave, abbreviated as CP wave, and also the transmittivity is obtain lower than -27 dB in the oblique incident angle from 0to 70, respectively. On the other hand, the transmittance in optics is obtained higher than 60%. Moreover, we study experimentally on the ETC system with placing this absorber between the ETC lane and the adjacent one. We measured the distribution of receiving power on the adjacent lane, when a water sprinkler existed on the ETC lane. As a result, it is confirmed that the receiving power on the adjacent lane could be realized lower than -70.5 dBm, and then a new improvement method has proven to be very useful in the ETC system.

  • Rejuvenating Communication Network System under Burst Arrival Circumstances

    Hiroyuki OKAMURA  Satoshi MIYAHARA  Tadashi DOHI  

     
    PAPER-Traffic Issues

      Vol:
    E88-B No:12
      Page(s):
    4498-4506

    Long running software systems are known to experience an aging phenomenon called software aging, one in which the accumulation of errors during the execution of software leads to performance degradation and eventually results in failure. To counteract this phenomenon a proactive fault management approach, called software rejuvenation, is particularly useful. It essentially involves gracefully terminating an application or a system and restarting it in a clean internal state. In this paper, we evaluate dependability performance of a communication network system with the software rejuvenation under the assumption that the requests arrive according to a Markov modulated Poisson process (MMPP). Three dependability measures, steady-state availability, loss probability of requests and mean response time on tasks, are derived through the hidden Markovian analysis based on the time-based software rejuvenation scheme. In numerical examples, we investigate the sensitivity of some model parameters to the dependability measures.

  • Absolutely Convergent Expansion of Hankel Functions for Sommerfeld Type Integral

    Bin-Hao JIANG  

     
    LETTER-Electromagnetic Theory

      Vol:
    E88-C No:12
      Page(s):
    2377-2378

    Generalized impedance boundary conditions are employed to simulate the effects of the parallel-stratified media on electromagnetic fields. Sommerfeld type integral contained in Hertz potential is expressed as the sum of two parts: zeroth order Hankel function and an absolutely convergent series expansion of spherical Hankel functions.

  • A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm

    Marcelo E. KAIHARA  Naofumi TAKAGI  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E88-A No:12
      Page(s):
    3610-3617

    A hardware algorithm for modular multiplication/division which performs modular division, Montgomery multiplication, and ordinary modular multiplication is proposed. The modular division in our algorithm is based on the extended Euclidean algorithm. We employ our newly proposed computation method that consists of processing the multiplier from the most significant digit first to calculate Montgomery multiplication. Finally, the ordinary modular multiplication is based on shift-and-add multiplication. Each of these three operations is carried out through the iteration of simple operations such as shifts and additions/subtractions. To avoid carry propagation in all additions and subtractions, the radix-2 signed-digit representation is employed. A modular multiplier/divider based on the algorithm has a linear array structure with a bit-slice feature and carries out n-bit modular multiplication/division in O(n) clock cycles, where the length of the clock cycle is constant and independent of n. This multiplier/divider can be implemented using a hardware amount only slightly larger than that of the modular divider.

  • Multiplier Energy Reduction by Dynamic Voltage Variation

    Vasily G. MOSHNYAGA  Tomoyuki YAMANAKA  

     
    PAPER-VLSI Circuit

      Vol:
    E88-A No:12
      Page(s):
    3548-3553

    Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a novel architectural technique to reduce power consumption of digital multipliers. Unlike related approaches which focus on multiplier transition activity reduction, we concentrate on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 1616-bit multiplier by 34% and 29% on peak and by 10% and 7% on average with area overhead of 15% and 4%, respectively, while maintaining the performance of traditional multiplier.

  • Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937

    Shiro KONUMA  Shuichi ICHIKAWA  

     
    LETTER-VLSI Systems

      Vol:
    E88-D No:12
      Page(s):
    2876-2879

    MT19937 is a kind of Mersenne Twister, which is a pseudo-random number generator. This study presents new designs for a MT19937 circuit suitable for custom computing machinery for high-performance scientific simulations. Our designs can generate multiple random numbers per cycle (multi-port design). The estimated throughput of a 52-port design was 262 Gbps, which is 115 times higher than the software on a Pentium 4 (2.53 GHz) processor. Multi-port designs were proven to be more cost-effective than using multiple single-port designs. The initialization circuit can be included without performance loss in exchange for a slight increase of logic scale.

  • Contour-Based Window Extraction Algorithm for Bare Printed Circuit Board Inspection

    Shih-Yuan HUANG  Chi-Wu MAO  Kuo-Sheng CHENG  

     
    PAPER-Pattern Recognition

      Vol:
    E88-D No:12
      Page(s):
    2802-2810

    Pattern extraction is an indispensable step in bare printed circuit board (PCB) inspection and plays an important role in automatic inspection system design. A good approach for pattern definition and extraction will make the following PCB diagnosis easy and efficient. The window-based technique has great potential in PCB patterns extraction due to its simplicity. The conventional window-based pattern extraction methods, such as Small Seeds Window Extraction method (SSWE) and Large Seeds Window Extraction method (LSWE), have the problems of losing some useful copper traces and splitting slanted-lines into too many small similar windows. These methods introduce the difficulty and computation intensive in automatic inspection. In this paper, a novel method called Contour Based Window Extraction (CBWE) algorithm is proposed for improvement. In comparison with both SSWE and LSWE methods, the CBWE algorithm has several advantages in application. Firstly, all traces can be segmented and enclosed by a valid window. Secondly, the type of the entire horizontal or vertical line of copper trace is preserved. Thirdly, the number of the valid windows is less than that extracted by SSWE and LSWE. From the experimental results, the proposed CBWE algorithm is demonstrated to be very effective in basic pattern extraction from bare PCB image analysis.

  • FDTD Analysis of Pulse Amplification in Er-Yb Codoped Garnet Crystal Waveguide-Type Optical Amplifier

    Nobuaki HIMENO  Nobuo GOTO  Yasumitsu MIYAZAKI  

     
    PAPER-EM Analysis

      Vol:
    E88-C No:12
      Page(s):
    2236-2242

    Waveguide-type optical amplifiers doped with Ytterbium and Erbium ions are theoretically studied. Sensitization of Er-doped amplifiers with Yb ion doping have many advantages such as the possibility of using broader pumping wavelength range and efficient pumping with smaller pumping power. Transient amplification characteristics of optical short pulses are numerically analyzed using FDTD method. The amplification characteristics are compared with the result of the steady state analysis using the rate equations.

  • Control of Total Transmission on Ferrite Edge-Mode Isolator

    Toshiro KODERA  

     
    PAPER-Microwaves, Millimeter-Waves

      Vol:
    E88-C No:12
      Page(s):
    2366-2371

    This paper introduces a new approach to realize a multi-state operation on the microwave isolator using ferrite edge-mode. The voltage control of total transmission on the isolator is realized. The operation is based on the unique property of ferrite edge-mode and the variable resistance of PIN diodes. On the isolator, the frequency response is investigated both experimentally and numerically. The numerical analysis is performed by the FDTD method. Both numerical and experimental results have shown that the transmission between two ports can be totally controlled by the applied voltage for the diodes. The experimental results indicate that the transmission direction can be controlled at 11 GHz, and the isolation ratio can be controlled for more than 30 dB.

  • An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences

    Takeshi MATSUMOTO  Hiroshi SAITO  Masahiro FUJITA  

     
    PAPER-Simulation and Verification

      Vol:
    E88-A No:12
      Page(s):
    3315-3323

    In this paper, an efficient equivalence checking method for two C descriptions is described. The equivalence of two C descriptions is proved by symbolic simulation. Symbolic simulation used in this paper can prove the equivalence of all of the variables in the descriptions. However, it takes long time to verify the equivalence of all of the variables if large descriptions are given. Therefore, in order to improve the verification, our method identifies textual differences between descriptions. The identified textual differences are used to reduce the number of equivalence checkings among variables. The proposed method has been implemented in C language and evaluated with several C descriptions.

  • A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures

    Toshiki KANAMOTO  Tetsuya WATANABE  Mitsutoshi SHIROTA  Masayuki TERAI  Tatsuya KUNIKIYO  Kiyoshi ISHIKAWA  Yoshihide AJIOKA  Yasutaka HORIBA  

     
    PAPER-Interconnect

      Vol:
    E88-A No:12
      Page(s):
    3463-3470

    This paper proposes a new non-destructive methodology to estimate physical parameters for LSIs. In order to resolve the estimation accuracy degradation issue for low-k dielectric films, we employ a parallel-plate capacitance measurement and a wire resistance measurement in our non-destructive method. Due to (1) the response surface functions corresponding to the parallel-plate capacitance measurement and the wire resistance measurement and (2) the searching of the physical parameter values using our cost function and simulated annealing, the proposed method attains higher precision than that of the existing method. We demonstrate the effectiveness of our method by application to our 90 nm SoC process using low-k materials.

  • A Design Algorithm for Sequential Circuits Using LUT Rings

    Hiroki NAKAHARA  Tsutomu SASAO  Munehiro MATSUURA  

     
    PAPER-Logic Synthesis

      Vol:
    E88-A No:12
      Page(s):
    3342-3350

    This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.

  • Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance

    Atsushi KUROKAWA  Masanori HASHIMOTO  Akira KASEBE  Zhangcai HUANG  Yun YANG  Yasuaki INOUE  Ryosuke INAGAKI  Hiroo MASUDA  

     
    PAPER-Interconnect

      Vol:
    E88-A No:12
      Page(s):
    3453-3462

    Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

  • Variable Frame Skipping Scheme Based on Estimated Quality of Non-coded Frames at Decoder for Real-Time Video Coding

    Tien-Ying KUO  

     
    PAPER-Image Processing and Video Processing

      Vol:
    E88-D No:12
      Page(s):
    2849-2856

    This paper proposes a block-based video encoder employing variable frame skipping (VFS) to improve the video quality in low bit rate channel. The basic idea of VFS mechanism is to decide and skip a suitable, non-fixed number of frames in temporal domain to reduce bit usage. The saved bits can be allocated to enhance the spatial quality of video. In literature, several methods of frame skipping decision have been proposed, but most of them only consider the similarities between neighboring coded frames as the decision criteria. Our proposed method takes into account the reconstruction of the skipped frames using motion-compensated frame interpolation at decoder. The proposed VFS models the reconstructed objective quality of the skipped frame and, therefore, can provide a fast estimate to the frame skipping at encoder. The proposed VFS can determine the suitable frame skipping in real time and provide the encoded video with better spatial-temporal bit allocation.

  • A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)

    Yuan-Long JEANG  Jer-Min JOU  Win-Hsien HUANG  

     
    PAPER-VLSI Architecture

      Vol:
    E88-A No:12
      Page(s):
    3531-3538

    In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing an application specific network on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN). First, a local bus is given for a group of IP cores so that the communications within this local bus can be arranged to be exclusive in time. If the communications of some IP cores should be required to be completed within a given amount of time, then a non-blocking MIN or a crossbar switch should be made for those IP cores instead of a bus. Then, a communication ratio (CR) for each pair of local buses is provided by users, and based on the Huffman coding philosophy, a process is applied to construct a binary tree (BT) with switches on the internal nodes and buses on the leaves. Since the binary tree system is deadlock free (no cycle exists in any path), the router is just a relatively simple and cheap switch. Simulation results show that the proposed methodology and architecture of NOC is better on switching circuit cost and performance than the SPIN and the mesh architecture using our developed deadlock-free router.

  • A New Method of Constructing a Set of Optimal Training Sequences in One-Dimensional CBSE

    Sung-Soo KIM  Jee-Hye KANG  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E88-B No:12
      Page(s):
    4682-4685

    In this paper, a new algorithm for the optimal training sequence with respect to sequence length in 1-dimensional cluster-based sequence equalizers (1-D CBSE) is presented. The proposed method not only removes the step of random training sequence selection but also shortens the length of the selected training sequences. The superiority of the new method is demonstrated by presenting several simulation results of quadrature phase shift keying (QPSK) signaling schemes and related analyses.

  • A Grammatical Approach to the Alignment of Structure-Annotated Strings

    Shinnosuke SEKI  Satoshi KOBAYASHI  

     
    PAPER-Automata and Formal Language Theory

      Vol:
    E88-D No:12
      Page(s):
    2727-2737

    In this paper, we are concerned with a structural ambiguity problem of tree adjoining grammars (TAGs), which is an essential problem when we try to model consensus structures of given set of ribonucleic acid (RNA) secondary structures by TAGs. RNA secondary structures can be represented as strings with structural information, and TAGs have a descriptive capability of this kind of strings, what we call structure-annotated strings. Thus, we can model RNA secondary structures by TAGs. It is sufficient to use existing alignment methods for just computing the optimal alignment between RNA secondary structures. However, when we also want to model the resulting alignment by grammars, if we adopt these existing methods, then we may fail in modeling the alignment result by grammars. Therefore, it is important to introduce a new alignment method whose alignment results can be appropriately modeled by grammars. In this paper, we will propose an alignment method based on TAG's derivations each corresponding to a given RNA secondary structure. For an RNA secondary structure, there exist a number of derivations of TAGs which correspond to the structure. From the grammatical point of view, the property of TAGs drives us to the question how we should choose a derivation from these candidates in order to obtain an optimal alignment. This is the structural ambiguity problem of TAGs, which will be mainly discussed in this paper. For dealing with this problem appropriately, we will propose an edit distance between two structure-annotated strings, and then present an algorithm which computes an optimal alignment based on the edit distance.

  • New Expressions for Coupling Coefficient between Resonators

    Ikuo AWAI  

     
    PAPER-Devices

      Vol:
    E88-C No:12
      Page(s):
    2295-2301

    Coupling between resonators are analyzed theoretically on basis of the coupled mode theory. New and basic equations for the coupling coefficient are derived and compared with those of waveguides. They should be useful for understanding the physical background of coupling and designing a new coupling scheme.

  • The Design of Diagnosis System in Maglev Train

    Zhigang LIU  

     
    PAPER

      Vol:
    E88-D No:12
      Page(s):
    2708-2714

    The diagnosis system of Maglev Train is one of most important parts, which can obtain kinds of status messages of electric and electronic devices in vehicle to ensure the whole train safety. In this paper, diagnosis system structure and diagnosis method are analyzed and discussed in detail. The disadvantages of diagnosis system are described. In virtue of the theory of ADS, some basic ideas of ADS are applied in new diagnosis system. The structure, component parts and diagnosis method of new diagnosis system are proposed, designed and discussed in detail. The analysis results show that new diagnosis not only embodies some ADS' ideas but also better meets the demands of Maglev Train Diagnosis System.

  • A Practical Approach to the Scheduling of Manufacturing System Using Fuzzy Optimization Technique

    Seung Kyu PARK  Kwang Bang WOO  

     
    LETTER-Computation and Computational Models

      Vol:
    E88-D No:12
      Page(s):
    2871-2875

    This paper presents a fuzzy optimization based scheduling method for the manufacturing systems with uncertain production capacities. To address the uncertainties efficiently, the fuzzy optimization technique is used in defining the scheduling problem. Based on the symmetric approach of fuzzy optimization and Lagrangian relaxation technique, a practical fuzzy-optimization based algorithm is developed. The computational experiments based on the real factory data demonstrate that the proposed method provides robust scheduling to hedge against uncertainties.

12361-12380hit(21534hit)