A novel PND (PMOS-NMOS-Depletion MOS) technology for a single poly gate non-volatile memory cell design has been reported for the first time. This technology features memory cell design with a differential cell architecture which enables to provide the higher performance for the key specifications such as programming time, erasing time, and endurance characteristics. This memory cell consists of 3-Transistors, PMOS, NMOS, and Depletion MOS transistors (hereafter PND). The DMOS in this cell is used for the tunneling device in the erasing operation, while the NMOS and the PMOS are used for the tunneling device and the coupling capacitor in the programming operation, respectively. The proposed PND design can allow lower applied voltage of the erase-gate (EG) and control-gate (CG) in the erasing and the programming operations so that the endurance characteristics can be improved because the DMOS suppresses the potential of floating-gate (FG) and hence the effective potential difference between the EG and the FG can be increased in the erasing operation. Based on the measured data, it can be expected that the erasing speed of the PND cell can be 125-fold faster than that of our previously reported work (PN type). Therefore, high performance and high reliability CMOS non-volatile memory without any additional process can be realized using this proposed PND technology.

Asymmetric Slope Dual Mode Differential Logic (ASDMDL) embodies high-speed dynamic and low-power static operations in a single design. Two-phase dual-rail logic signaling is used in a high-speed operation, where a logical evaluation is preceded by pre-charge, and it asserts one of the rails with an asymmetrically shortened rise transition to express a binary result. On the other hand, single-phase differential logic signaling eliminates pre-charge and leads to a low-power static operation. The operation mode is defined by the logic signaling styles, and no control signal is needed in the logic cell. The design of mixed CMOS and ASDMDL logic circuits can be automated with general logic synthesis and place-and-route techniques, since the physical ASDMDL cell is prepared in such a way to comply with a CMOS standard-cell design flow. A mixed ASDMDL/CMOS micro-processor in a 0.18-µm CMOS technology demonstrated 232 MHz operation, corresponding to 14% speed improvement over a full CMOS implementation. This was achieved by substituting ASDMDL cells for only 4% of the CMOS logic cells in data paths. The low-speed operation of ASDMDL at 100 MHz was nearly equivalent to that of CMOS. However, power consumption was reduced by 3% due to the use of ASDMDL complex logic cells. Area overhead was less than 4%.

This paper presents a novel threshold-based selection scheme to combine adaptive transmit antenna selection with an adaptive quadrature amplitude modulation (AQAM) for a spatial multiplexing (SM) multiple-input multiple-output (MIMO) system with linear receivers in practical uncorrelated and correlated channel conditions. The proposed scheme aims to maximize the average spectral efficiency (ASE) for a given bit error rate (BER) constraint and also to lower the hardware complexity. Our simulations are run on a general MIMO channel model, under the assumption that the channel state information (CSI) is known at the receiver and the adaptive control signaling can be perfectly fed back to the transmitter. We deploy the low rank-revealing QR (LRRQR) algorithm in transmit antenna subset selection. LRRQR is computationally less expensive than a singular value decomposition (SVD) based algorithm while the two algorithms achieve similar error rate performances. We show that both the conventional AQAM scheme (i.e., without adaptive transmit antenna selection) and the SM scheme perform poorly in a highly correlated channel environment. We demonstrate that our proposed scheme provides a well-behaved trade-off between the ASE and BER under various channel environments. The ASE (i.e., throughput) can be maximized with a proper choice of the channel quality threshold and AQAM mode switching threshold levels for a target BER.

Spatial multiplexing (SM) offers a linear increase in transmission rate without bandwidth expansion or power increase. In SM systems, the LMMSE receiver establishes a good tradeoff between the complexity and performance. The performance of the LMMSE receiver would be degraded by MIMO channel estimation errors. This letter focus on obtaining the asymptotic convergence of output interference power and SIR performance for the LMMSE receiver with channel uncertainty. Exactly matched simulation results verify the validity of analysis in the large-system assumption. Furthermore, we find that the analytical results are also valid in the sense of average results for limited-scale system in spite of the asymptotic assumption used in derivation.

This paper presents a high-speed 5454-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 µm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.

Assume that each vertex of a graph G is assigned a constant number q of nonnegative integer weights, and that q pairs of nonnegative integers li and ui, 1 ≤ i ≤ q, are given. One wishes to partition G into connected components by deleting edges from G so that the total i-th weights of all vertices in each component is at least li and at most ui for each index i, 1 ≤ i ≤ q. The problem of finding such a "uniform" partition is NP-hard for series-parallel graphs, and is strongly NP-hard for general graphs even for q = 1. In this paper we show that the problem and many variants can be solved in pseudo-polynomial time for series-parallel graphs and partial k-trees, that is, graphs with bounded tree-width.

In D.O.A. estimation, identification of the signal and the noise subspaces plays an essential role. This identification process was traditionally achieved by the eigenvalue decomposition (EVD) of the spatial correlation matrix of observations or the generalized eigenvalue decomposition (GEVD) of the spatial correlation matrix of observations with respect to that of an observation noise. The framework based on the GEVD is not always an extension of that based on the EVD, since the GEVD is not applicable to the noise-free case which can be resolved by the framework based on the EVD. Moreover, they are not applicable to the case in which the spatial correlation matrix of the noise is singular. Recently, a quotient-singular-value-decomposition-based framework, that can be applied to problems with singular noise correlation matrices, is introduced for noise reduction. However, this framework also can not treat the noise-free case. Thus, we do not have a unified framework of the identification of these subspaces. In this paper, we show that a unified framework of the identification of these subspaces is realized by the concept of proper and improper eigenspaces of the spatial correlation matrix of the noise with respect to that of observations.

In this letter, the system capacity of multiuser diversity combined with spatial multiplexing schemes is analyzed. An analytic expression is derived for the ergodic system capacity with multiuser scheduling and dual multi-input multi-output (MIMO) systems by using a tight lower bound of the link capacity. The proposed analytic approach is verified through comparisons between analytic and simulated results, and is shown to make fairly precise predictions of the ergodic system capacity and the scheduling gains even when the numbers of antennas and users are small.

Optically controlled beam forming techniques are effective for phased-array antenna control. We have developed the Fourier transform optical beamformer (FT-OBF). The antenna radiation pattern inputted into an amplitude spatial light modulator (A-SLM) is optically Fourier transformed to a specific phase-front light beam equivalent to an antenna excitation in the FT-OBF. Optical signal processing, used the Fourier transform optics, is effective to large-scale, two-dimensional, and high-speed signal processing. To implement a flexible and finer antenna beam pattern control, we use an A-SLM as input image formation of the FT optics. And, to realize a small-size FT-OBF, we use symmetric triplet lenses with convex, concave and convex lens. The total optical system becomes below 1/5 length compared with the length using single lens. Finally, we evaluated the developed FT-OBF with the generated amplitude and phase distributions, which excitation signal of an array antenna. We measured an antenna radiation beam pattern, beam steering and beam width control, in the C-band. Measurement results agreed with theoretical calculated results. These results show the feasibility of the spatial light modulator based FT-OBF.

This paper proposes a two-dimensional self-matching receiver for Free Space Optics (FSO) communication system using chaotic spatial synchronization. This system is able to obtain the information of two-dimensional code from received pattern. This paper considers that proposed system is applied to two applications. The first application is image transmission. This paper shows that applying proposed system to image transmission enables to restore the desired image, which doesn't require strict alignment of receiver, and evaluates transmission optical power. The second application is Code Division Multiplexing (CDM). This paper shows that applying proposed system to CDM system enables to demodulate desired digital signals regardless of the uncertainty of received position. Moreover, the required transmission optical power and bit error rate performance are obtained by computer simulation.

In this paper, we investigate an efficient user selection and sub-band allocation algorithm in which each user transmits two-step partial CQI to reduce the amount of feedback in multi-user downlink OFDMA systems. Simulation results show that we can greatly reduce the feedback rate at the expense of negligible performance degradation compared to the full CQI feedback schemes or that we can greatly improve the performance with slightly reduced feedback rate compared to conventional partial CQI feedback schemes.

In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate, and are naturally applicable to various actual devices for simulating power analysis. Furthermore, we demonstrate the weakness of previously known hardware countermeasures for both our model and FPGA and suggest secure conditions for the hardware countermeasure.

In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.

This paper proposes novel calculuses of linearizing attack that can be applied to higher order differential attack. Higher order differential attack is a powerful and versatile attack on block ciphers. It can be roughly summarized as follows: (1) Derive an attack equation to estimate the key by using the higher order differential properties of the target cipher, (2) Determine the key by solving an attack equation. Linearizing attack is an effective method of solving attack equations. It linearizes an attack equation and determines the key by solving a system of linearized equations using approaches such as the Gauss-Jordan method. We enhance the derivation algorithm of the coefficient matrix for linearizing attack to reduce computational cost (fast calculus 1). Furthermore, we eliminate most of the unknown variables in the linearized equations by making the coefficient column vectors 0 (fast calculus 2). We apply these algorithms to an attack of the five-round variant of KASUMI and show that the attack complexity is equivalent to 228.9 chosen plaintexts and 231.2 KASUMI encryptions.

This paper considers a more generalized capacitor that can decrease its width using its own electrical force. We consider a model in which the capacitor with plate distance d is coupled with repulsive mechatronical potential energy, which is proportional to 1/dn. In the conventional case, n is considered to be approximately very large. In our capacitor model, there is a stable point between attractive electrical force and repulsive mechatronical force. In this system, electrostatic energy is equal to the sum of mechatronical potential energy and energy dissipation. Moreover, the mechatronical potential energy is 1/n times smaller than the electrostatic energy. All energies, including the electrostatic energy, potential energy, and energy dissipation, are proportional not to ordinary value V2, but to V2/(n-1)+2, where V is the power supply voltage. This means the voltage dependence of energy is unusual. It is strongly dependent on the capacitor matter, i.e., on the characteristics of the mechatronical system. In addition, the energy dissipation of the system can be reduced to zero using the adiabatic charging process.

Differential power analysis (DPA) is an effective technique that extracts secret keys from cryptographic systems through statistical analysis of the power traces obtained during encryption and decryption operations. This letter proposes symmetric discharge logic (SDL), a circuit-level countermeasure against DPA, which exhibits uniform power traces for every clock period by maintaining a set of discharge paths independent of input values. This feature minimizes differences in power traces and improves resistance to DPA attacks. HSPICE simulations for the test circuits using 0.18 µm TSMC CMOS process parameters indicate that SDL reduces power differences by an order of magnitude, compared to the existing circuit-level technique.

This paper presents two hardware-friendly low-power oriented fast motion estimation (ME) algorithms and their VLSI implementations. The basic idea of the proposed partial distortion sorting (PDS) algorithm is to disable the search points which have larger partial distortions during the ME process, and only keep those search points with smaller ones. To further reduce the computation overhead, a simplified local PDS (LPDS) algorithm is also presented. Experiments show that the PDS and LPDS algorithms can provide almost the same image quality as full search only with 36.7% computation complexity. The proposed two algorithms can be integrated into different FSBMA architectures to save power consumption. In this paper, the 1-D inter ME architecture [12] is used as an detailed example. Under the worst working conditions (1.62 V, 125) and 166 MHz clock frequency, the PDS algorithm can reduce 33.3% power consumption with 4.05 K gates extra hardware cost, and the LPDS can reduce 37.8% power consumption with 1.73 K gates overhead.

This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each gate and suppresses the propagation of glitch to allow power consumption to be independent of predictable data. Furthermore, we implement basic logic circuits on the FPGA (Field Programmable Gate Array) by using RSL, and evaluate the effectiveness. As a result, we confirm the fact that the secure circuit can be structured against DPA and Second-Order DPA.

In this letter, we suggest a noise estimation method which can be applied for speech enhancement in various noise environments. The proposed method consists of the following two main processes to analyze and estimate efficiently the noise from the noisy speech. First, a least-squares line is used, which is obtained by applying coefficient magnitudes in node with a uniform wavelet packet transform to a least squares method. Next, a differential forgetting factor and a correlation coefficient per subband are applied, where each subband consists of several nodes with the uniform wavelet packet transform. In particular, this approach has the ability to update noise estimation by using the estimated noise at the previous frame only instead of employing the statistical information of long past frames and explicit nonspeech frames detection consisted of noise signals. In objective assessments, we observed that the performance of the proposed method was better than that of the compared methods. Furthermore, our method showed a reliable result even at low SNR.

We demonstrate single electron counting on an alkanethiol-protected Au nanodot in a double-barrier tunneling structure by noncontact atomic-force spectroscopy (nc-AFS). The Coulomb step width dependence on the Au nanodot diameter is observed. Evaluation of fractional charge Q0 and contact potential difference by nc-AFS reveals a Vd-independent voltage shift due to Q0.