In this letter, we suggest a noise estimation method which can be applied for speech enhancement in various noise environments. The proposed method consists of the following two main processes to analyze and estimate efficiently the noise from the noisy speech. First, a least-squares line is used, which is obtained by applying coefficient magnitudes in node with a uniform wavelet packet transform to a least squares method. Next, a differential forgetting factor and a correlation coefficient per subband are applied, where each subband consists of several nodes with the uniform wavelet packet transform. In particular, this approach has the ability to update noise estimation by using the estimated noise at the previous frame only instead of employing the statistical information of long past frames and explicit nonspeech frames detection consisted of noise signals. In objective assessments, we observed that the performance of the proposed method was better than that of the compared methods. Furthermore, our method showed a reliable result even at low SNR.

Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet the above requirements. In this paper, we propose methods for finding as many Xs as possible in test sequences for sequential circuits. Given a fully specified test sequence generated by a sequential ATPG, the proposed methods produce a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence. The methods apply an approach based on fault simulation, and they introduce some heuristics for reducing the simulation effort. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of the proposed methods.

In this letter, it is shown that a MAP detector can be employed with differential pulse-position modulation (L-DPPM) in an indoor optical wireless system. The MAP detector error performance is evaluated and compared with that of a hard-decision detector and MLSD over an intersymbol interference channel. It is shown that a MAP detector provides superb performance even in a dispersive channel with high DT.

Fundamental limitation on assisting a write margin (WRTM) by reducing the cell terminal bias (VDDM) has been made clear for the first time and the new cell terminal biasing scheme featuring a differential VDDM (Diff-VDDM) control has been proposed to address the issues which the conventional schemes proposed so far can not overcome [1]-[5]. Since Diff-VDDM biasing scheme can meet the both of the requirements simultaneously of 1) reducing drivability for the PMOS load transistor on the "Low" written bit-line (BL) side, and 2) increasing drivability for the other side PMOS for a write recovery, it can provide a lower minimum operating voltage (Vdd_min) for the write operation even if considering a sufficiently-large random threshold voltage (Vth) variations. The following points have been shown based on an actual 65 nm CMOS device variation data and the implemented layout data that 1) Vdd_min for the write operation can be lowered from Vdd=1.1 V down to 0.8 V when considering a 4-sigma (σ) variation, 2) the write recovery time can be reduced by 92% and 70% that for the conventional schemes [1],[2] at Vdd=0.7 V and 1.0 V, respectively, and 3) WRTM defined by the percentage (%) of the required (BL pull-down level/Vdd) to flip the cell nodes for the write operation can be relaxed by 2.6-fold and 1.4-fold that for the conventional schemes [1],[2] at Vdd=0.75 V and 1.0 V, respectively. As an actual implementation in a 65 nm CMOS, a 32-kbit single-port SRAM macro design and the measured butterfly curves have been demonstrated.

A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.

Recently, lattice reduction aided (LRA) detectors have been introduced into Vertical Bell-Labs Layered Space-Time (V-BLAST) systems to obtain nearly optimal bit error rate (BER) performance for only small additional complexity. In this paper, the layer error characteristics of LRA-V-BLAST detectors are investigated and compared with those of conventional V-BLAST ones. Two important conclusions are drawn for the LRA-V-BLAST detectors. First, the variation of their mean square error (MSE) within each detection iteration is not as large as in conventional V-BLAST detectors. Second, thanks to lattice reduction there exists an inherent sub-optimal detection order from the last to the first layer. These conclusions allow LRA-V-BLAST detectors to avoid optimal ordering to further reduce the complexity. LRA-V-BLAST detectors without optimal ordering are shown to obtain almost the same BER performance of LRA-V-BLAST detector with optimal ordering.

The multi-step prediction model based on partial least squares (PLS) is established to predict short-term load series with high embedding dimension in this paper, which refrains from cumulative error with local single-step linear model, and can cope with the multi-collinearity in the reconstructed phase space. In the model, PLS is used to model the dynamic evolution between the phase points and the corresponding future points. With research on the PLS theory, the model algorithm is put forward. Finally, the actual load series are used to test this model, and the results show that the model plays well in chaotic time series prediction, even if the embedding dimension is selected a big value.

The decorrelating detector is one of the detecting methods in a direct sequence code division multiple access systems. We investigate the blind adaptive decorrelating detector (BADD) using only the signature of the desired user (DU) according to the assumption that the algorithm is used in downlink. When the BADD is constructed with an antenna array, both the spatial and temporal signature must be taken into consideration for signal detection. We propose the BADD incorporated with the blind estimation of spatial signature (SS) of the DU only from the received signals. As the estimation procedure of SS, the orthogonal projection approximation and subspace tracking algorithm is adopted. The proposed BADD presented the BER improvement with using antenna array. The BER performance has a lower limit with increasing the number of antenna array elements.

This paper proposes a wideband speech coder in which a G.711 bitstream is embedded. This coder has an advantage over conventional coders in that it has a high interoperability with existing terminals so costly transcoding involving decoding and re-encoding can be avoided. We also propose a partial mixing method that effectively reduces the mixing complexity in multiple-point remote conferences. To reduce the complexity, we take advantage of the scalable structure of the bitstream and mix only the lower band of the signal. For the higher band, the main speaker location is selected among remote locations and is redistributed with the mixed lower-band signal. By subjective evaluations, we show that the speech quality can be maintained even when the speech signals are partially mixed.

The proportional delay differentiation (PDD) model provides consistent packet delay differentiation between classes of service. Currently, the present schedulers performing the PDD model cannot achieve desired delay proportion observed in short timescales under light/moderate load. Thus, we propose a Non-Work-Conserving (NWC) scheduler, which utilizes the pseudo-waiting time for an empty queue and forces each class to compare its priority with those of all other classes. Simulation results reveal that NWC outperforms all current schedulers in achieving the PDD model. However, NWC suspends the server from transmitting packets immediately if an empty class has the maximum priority, resulting in an idle server. Therefore, we further propose two approaches, which will serve a best-effort class during this idle time. Compared with other schedulers, the proposed approaches can provide more predictable and controllable delay proportion, accompanied with satisfactory throughput and average queuing delay.

Nonlinear modeling of complex irregular systems constitutes the essential part of many control and decision-making systems and fuzzy logic is one of the most effective algorithms to build such a nonlinear model. In this paper, a new approach to fuzzy modeling is proposed. The model considered herein is the well-known Sugeno-type fuzzy system. The fuzzy modeling algorithm suggested in this paper is composed of two phases: coarse tuning and fine tuning. In the first phase (coarse tuning), a successive clustering algorithm with the fuzzy validity measure (SCFVM) is proposed to find the number of the fuzzy rules and an initial fuzzy model. In the second phase (fine tuning), a moving genetic algorithm with partial encoding (MGAPE) is developed and used for optimized tuning of membership functions of the fuzzy model. Two computer simulation examples are provided to evaluate the performance of the proposed modeling approach and compare it with other modeling approaches.

In the execution on a smart card, side channel attacks such as the simple power analysis (SPA) and the differential power analysis (DPA) have become serious threat. Side channel attacks monitor the side channel information such as power consumption and even exploit the leakage information related to power consumption to reveal bits of a secret key d although d is hidden inside a smart card. Almost public key cryptosystems including RSA, DLP-based cryptosystems, and elliptic curve cryptosystems execute an exponentiation algorithm with a secret-key exponent, and they thus suffer from both SPA and DPA. In the case of elliptic curve cryptosystems, DPA is improved to the refined power analysis (RPA), which exploits a special point with a zero value and reveals a secret key. RPA is further generalized to zero-value register attack (ZRA). Both RPA and ZRA utilize a special feature of elliptic curves that happens to have a special point or a register used in addition and doubling formulae with a zero value and that the power consumption of 0 is distinguishable from that of a non-zero element. To make the matters worse, some previous efficient countermeasures to DPA are neither resistant to RPA nor ZRA. This paper focuses on elegant countermeasures of elliptic curve exponentiations against RPA, ZRA, DPA and SPA. Our novel countermeasure is easily generalized to be more efficient algorithm with a pre-computed table.

Visual criteria for diagnosing liver diseases, such as cirrhosis, from ultrasound images can be assisted by computerized texture classification. This paper proposes a system applying a PNN (Pyramid Neural Network) for classifying the hepatic parenchymal diseases in ultrasonic B-scan texture. In this study, we propose a multifractal-dimensions method to select the patterns for the training set and the validation sets. A modified box-counting algorithm is used to calculate the dimensions of the B-scan images. FDWT (Fast Discrete Wavelet Transform) is applied for feature extraction during the preprocessing. The structure of the proposed neural network is testified by training and validation sets by cross-validation method. The performance of the proposed system and a system based on the conventional multilayer network architecture is compared. The results show that, compared with the conventional 3-layer neural network, the performance of the proposed pyramid neural network is improved by efficiently utilizing the lower layer of the neural network.

To provide basic considerations for the realization of methods for predicting the electromagnetic (EM) radiation from a printed circuit board (PCB) with plural signal traces driven in the even-mode, the characteristics of the EM radiation resulting from two signal traces on a PCB are investigated experimentally and by numerical modeling. First, the frequency responses of common-mode (CM) current and far-electric field as electromagnetic interference (EMI) are discussed. As the two traces are moved closer to the PCB edge, CM current and far-electric field increase. The frequency responses in the two signal trace case can be identified using insights gained from the single trace case. Second, to understand the details of the increase in CM current, the distribution of the current density on the ground plane is calculated and discussed. Although crosstalk ensues, the rule for PCB design is to keep two high-speed traces on the interior of the PCB whenever possible, from the point of view of EM radiation. Finally, an empirical formula to quantify the relationship between the positions of two traces and CM current is provided and discussed by comparing four different models. Results calculated with the empirical formula and finite-difference time-domain (FDTD) modeling are in good agreement, which indicates the empirical formula may be useful for developing EMI design guidelines.

Spatial despreading weight based on minimum mean square error (MMSE) criterion is derived for orthogonal space-time spreading transmit diversity (OSTSTD) in a fast fading channel, taking into account the inter-antenna interference (IAI) and the inter-code interference (ICI) caused by orthogonality distortion of time-domain spreading codes. Average bit error rate (BER) performance is theoretically analyzed and confirmed by computer simulation to show that the diversity gain can be obtained even in a fast fading.

We present room temperature current voltage characteristics from SiGe interband tunneling diodes epitaxially grown on highly resistive Si(001) substrates. In this case, a maximum peak to valley current ratio (PVCR) of 5.65 was obtained. The possible integration of a SiGe tunnel diode with a strained Si transistor lead us to investigate the growth of SiGe interband tunneling diodes on Si0.7Ge0.3 virtual substrates. A careful optimization of the layer structure leads to a maximum PVCR of 1.36 at room temperature. The latter value can be further increased to 2.26 at 3.7 K. Our results demonstrate that high quality SiGe interband tunneling diodes can be realized, which is of great interest for future memory and high speed applications.

In this paper we propose a road object extraction technique based on an active contour model (snake) considering inertia and differential features in a movie. Different energy functions can be applicable to snake in order to use information of various objects and various environments. Using many methods for tracking a moving object, snake can be applied to a scene frame by frame. Initial positions of the control points in a frame can refer to the results in the previous frame. We focus on the inertia that works between object shapes in the previous and present frames. In this research inertia is the tendency of a control point to resist its changes in its state of motion in an image space. We introduce an external energy for snake based on inertia of control points. Internal energy functions based on differential features of road geometry are also introduced to extract straight, circular and S-shaped road segments smoothly. The proposed method is applied to extract road geometry from a movie taken by a camera equipped on the flont of a vehicle. Experimental results indicate the availability of the proposed method which is to extract road geometry smoothly and to improve its robustness.

Fast and accurate power bus designer (FAPUD) for multi-layers high-speed digital boards is the power supply network design tool for accurate and precise high speed board. FAPUD is constructed based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching in can be carried out because the I/O switching effect on a power supply noise can estimate for the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

If a logic circuit was specialized to a specific input, the derived circuit would be faster and smaller than the original. This study presents various designs of a key-specific AES encryption circuit. In our iterative design, 41% of the logic gates and 20% of RAM were reduced, while 24% more performance was derived. In our pipelined design, 54% of the logic gates and 20% of RAM were reduced, while 74% higher performance was achieved. The results on DES encryption circuits are also presented for comparison.