We propose a new and fast full search (FS) motion estimation algorithm for video coding. The computational reduction comes from sequential rejection of impossible candidates with derived formula and subblock norms. Our algorithm reduces more the computations than the recent fast full search (FS) motion estimation algorithms.

In order to maintain the diversity of structures in the population and prevent premature convergence, I have developed a new genetic algorithm called DCGA. In the experiments on many standard benchmark problems, DCGA showed good performances, whereas with harder problems, in some cases, the phenomena were observed that the search was stagnated at a local optimum despite that the diversity of the population is maintained. In this paper, I propose methods for escaping such phenomena and improving the performance by reinitializing the population, that is, a method called each-structure-based reinitializing method with a deterministic structure diverging procedure as a method for producing new structures and an adaptive improvement probability bound as a search termination criterion. The results of experiments demonstrate that DCGA becomes robust in harder problems by employing these proposed methods.

We summarize recent studies on performance improvement in the correlation-based continuous-wave technique for optical fiber distributed strain measurement using Brillouin scattering, that had been proposed previously. The correlation-based technique enables the spatial resolution of 1 cm, which is difficult for conventional sensing techniques using Brillouin scattering to achieve. Though the correlation-based technique left a problem with measurement range, we have proposed methods to overcome it with keeping high spatial resolution. In addition, we verified usefulness of the technique for smart materials by measuring strain distribution along surface of a ring structure.

This report describes a new methodology for the optimal placement of decoupling capacitors on the printed circuit board (PCB). This method searches the optimal position of decoupling capacitor so that the impedance characteristics at the power supply is minimized in the specified frequency range. In this method, the PCB is modeled by the PEEC method to handle the 3-dimensional structures and Krylov-subspace technique is applied to obtain efficiently the impedance characteristics in the frequency domain.

Partially depleted SOI technology with body-tied hybrid trench isolation was developed in order to counteract floating body effects which offers negative impact on the drive current of transistors and the stability of circuit operation while maintaining SOI's specific merits such as high speed operation and low power consumption. The feasibility of this technology and its superior soft error effects were demonstrated by a fully functional 4M-bit SRAM. Its radio frequency characteristics were also evaluated and it was verified that high-performance transistors and passive elements can be realized by the combination of the SOI structure and a high-resistivity substrate. Moreover, its application to a 2.5 GHz digital IC for optical communication was also demonstrated. Thus it was proven that the body-tied SOI devices with the hybrid trench isolation is suitable to realize intelligent and reliable high-speed system-on-a chip integrating various IP's.

This paper describes the JAINTM JavaTM Call Control (JCC) Application Programming Interface (API), and its relationship to network protocols, in particular the Session Initiation Protocol (SIP). JCC is a high-level object-oriented open, standard API for Next Generation Network (NGN) softswitches that enables rapid creation, by third parties, of services that can run independently of the underlying network technology (e.g. wireless, wired, packet, IP, PSTN) and protocols. SIP is a protocol that has been proposed for a wide variety of uses in IP networks, including call control. We argue that instead of being competitors, JCC and SIP are complementary, with JCC offering higher-layer programming abstractions and protocol-independence, and demonstrate by examples how to map JCC version 1.0 to a SIP environment. We thus show that for common call control applications using JCC is simpler, faster and less maintenance intensive than using SIP directly.

Antialiased is one of challenging problems to be solved for the high fidelity image synthesis in 3D graphics. In this paper a rasterization processor which is capable of single-pass full-screen antialiasing is presented. To implement a H/W accelerated single-pass antialiased rasterization processor at the reasonable H/W cost and minimized processing performance degradation, our work is mainly focused on the efficient H/W implementation of a modified version of the A-buffer algorithm. For the efficient handling of partial-pixel fragments of the rasterization phase, a new partial-pixel-merging scheme and a simple and efficient new dynamic memory management scheme are proposed. For the final blending of partial-pixels without loss of generality, a parallel subpixel blender is introduced. To study the feasibility of the proposed rasterization processor as a practical rasterization processor, a prototype processor has been designed using a 0.35 µm EML technology. It operates 100 MHz @3.3 V and has the rendering performance from 25M to 80M pixel-fragments/sec depending on the scene complexity.

A digital noncoherent demodulation scheme is presented for reception of Gaussian frequency shift keying (GFSK) signals with small modulation index. The proposed differential demodulator utilizes oversampled signals to estimate the symbol timing and to compensate the frequency offset. The performance of the proposed receiver is evaluated in terms of the bit-error rate (BER). Numerical results show that the proposed demodulator provides performance comparable to that of conventional baseband differential demodulator, while significantly reducing the implementation complexity suitable for single chip integration with direct conversion radio frequency module. Finally the performance of the proposed receiver is improved by adding a simple decision feedback module.

Deterministic execution testing has been considered a promising way for concurrent program testing because of its ability to replay a program's execution. Since, however, deterministic execution requires that a synchronization event sequence to be replayed be feasible and valid, it is not directly applicable to a situation in which synchronization sequences, being valid but infeasible, are taken into account. Resolving this problem is very important because a program may still meet its specification although the feasibility of all valid sequences is not satisfied. In this paper, we present a new approach to deterministic execution for testing concurrent systems. The proposed approach makes use of the notion of event independence and constructs an automation which accepts all the sequences semantically equivalent to a given event sequence to be replayed. Consequently, we can allow a program to be executed according to event sequences other than the given (possible infeasible) sequence if they can be accepted by the automation.

Recently a high-resolution image that has more than one million pixels is available easily. However, such an image requires much processing time and memory for an image understanding system. In this paper, we propose an integrated image understanding system of multi-resolution analysis and multi-agent-based architecture for high-resolution images. The system we propose in this paper has capability to treat with a high-resolution image effectively without much extra cost. We implemented an experimental system for images of indoor scenes.

We examine diagnosis of processor array systems formed as two-dimensional grids, with boundaries, and either four or eight neighbors for each interior processor. We employ a parallel test schedule. Neighboring processors test each other and report the results. Our diagnostic objective is to find a fault-free processor or set of processors. The system may then be sequentially diagnosed by repairing those processors tested faulty according to the identified fault-free set. We establish an upper bound on the maximum number of faults that can be sustained without invalidating the test results under worst case conditions. We give test schedules and diagnostic algorithms that meet the upper bound as far as the highest order term. We compare these near optimal diagnostic algorithms to alternative algorithms--both new and already in the literature.

As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.

In this paper, we study nonblocking supervisory control of discrete event systems under partial observation. We introduce a weak normality condition defined in terms of a modified natural projection map. The weak normality condition is weaker than the original one and stronger than the observability condition. Moreover, it is preserved under union. Given a marked language specification, we present a procedure for computing the supremal sublanguage which satisfies Lm(G)-closure, controllability, and weak normality. There exists a nonblocking supervisor for this supremal sublanguage. Such a supervisor is more permissive than the one which achieves the supremal Lm(G)-closed, controllable, and normal sublanguage.

The legal firing sequence problem of Petri nets (LFS) is one of fundamental problems in the analysis of Petri nets, because it appears as a subproblem of various basic problems. Since LFS is shown to be NP-hard, various heuristics has been proposed to solve the problem of practical size in a reasonable time. In this paper, we propose a new algorithm for this problem. It is based on the partial order verification technique, and reduces redundant branches in the search tree. Moreover, the proposed algorithm can be combined with various types of heuristics.

We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.

The IETF Differentiated Services (DiffServ) framework achieves scalability by (1) aggregating traffic flows with coarse grain QoS on the data plane, and (2) allocating network resources with a bandwidth broker (BB) on the control plane. However, there are many issues that need to be addressed under such framework. First, it has been shown that the concatenation of strict priority (SP) scheduler of class-based queues (CBQ) can cause delay jitter unbounded under certain utilization, which is not acceptable to support the premium service (PS). Furthermore, it is not clear how such a DiffServ network can support traffic flows requiring the guaranteed service (GS), which is a desirable feature of the future Internet. This paper presents architecture and mechanisms to support multiple QoS under the DiffServ paradigm. On the data plane, we present a node architecture based on the virtual time reference system (VTRS). The key building block of our node architecture is the core-stateless virtual clock (CSVC) scheduling algorithm, which, in terms of providing delay guarantee, has the same expressive power as a stateful weighted fair queueing (WFQ) scheduler. With the CSVC scheduler as our building block, we design a node architecture that is capable of supporting integrated transport of the GS, the PS, the assured service (AS), and the traditional best effort (BE) service. On the control plane, we present a BB architecture to provide flexible resource allocation and QoS provisioning. Simulation results demonstrate that our architecture and mechanisms can provide scalable and flexible transport of integrated traffic of the GS, the PS, the AS, and the BE services.

A method is described that can allocate bandwidth to each user flow fairly in a scalable network architecture such as differentiated services architecture. As promising queueing techniques for providing differentiated services, class-based packet scheduling and selective packet discarding have been attracting attention. However, if we consider that bandwidth should be allocated to each flow in a weighted manner, the parameters used in these methods such as the weight assigned to each class queue should be pre-determined appropriately based on an assumption about the number of flows in each class. Thus, when the actual traffic pattern differs from the assumed one, they may not work well. Instead of assuming the traffic conditions, our method estimates the number of active flows in each class by simple traffic measurement and dynamically changes the weight assigned to each class queue based on the estimated number. Our method does not need to maintain the per-flow state, which gives it scalability. Simulation showed that this method is effective under various patterns of the number of active flows.

This paper introduces a switched-voltage delay cell with differential inputs. It can be used as a building block for a range of analogue functions such as voltage-to-frenquency converter, A/D converter, etc. Applications incorporating the delay cell are presented. The performances are verified by simulations on PSpice.

In this paper, we present a numerical method with guaranteed accuracy to solve initial value problems (IVPs) of normal form simultaneous first order ordinary differential equations (ODEs) which have wide domain. Our method is based on the algorithm proposed by Kashiwagi, by which we can obtain inclusions of exact values at several discrete points of the solution curve of ODEs. The method can be regarded as an extension of the Lohner's method. But the algorithm is not efficient for equations which have wide domain, because the error bounds become too wide from a practical point of view. Our purpose is to produce tight bounds even for such equations. We realize it by combining Kashiwagi's algorithm with the mean value form. We also consider the wrapping effects to obtain tighter bounds.

Dual FDTS/DF detector is an advanced version of FDTS/DF detector that gives significant performance improvement over FDTS/DF scheme on linear channels, and moreover, in contrast to other dual-detector schemes, it is suitable for various d-constraint coded channels. As recording density increases, channel nonlinearities such as non-linear transition shift (NLTS) and partial erasure (PE) degrade the performance of detectors. In this paper, we use nonlinear channel models to study the BER performance of dual FDTS/DF detector and compare the performances with those of other detectors through bit-by-bit simulations. Simulation results show that the dual FDTS/DF detector is superior in performance compared to FDTS/DF and MDFE detectors even on nonlinear channels, and it gives comparable BER performance with M2DFE (adv.) on nonlinear channels. Results also indicate that the detectors on the d=1 coded channels are more robust to channel nonlinearities compared to those of other detectors (such as PRML family detectors) on the d=0 coded channels.