We report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1-µm gate HEMT was 430 mS/mm and the peak-to-valley current ratio of the RTD was 5.1. Using the integrated structure, we demonstrate basic digital circuits to show low power characteristics of an RTD-load inverter and a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V. The static power consumption was 7.3 µW/gate for the inverter and 3.0 µW for memory cell.

Recently as one of attractive applications in the B-ISDN era, LAN/MAN interconnection through an ATM network has been coming up because burstiness of LAN/MAN data traffic is applicable to distinctive features of cell based ATM network. In order to overcome a difference of the connection mode, i.e., CL packet transfer of LAN/MAN and CO cell transfer of ATM network, a number of interworking and bandwidth allocation mechanisms have been proposed. These methods, however, indicate both merits and drawbacks concerning with CL data transfer quality, network resource efficiency and processing overhead in IWU/CLS and the network, and have been mostly evaluated only for a single IWU model. This paper aims at showing the most appropriate method of LAN/MAN interworking for IWU-IWU or IWU-CLSF connection. In the paper, some interworking issues including a general qualitative assessment are clarified. We then evaluate the selected five interworking methods based on Bandwidth Renegotiation (BR) and VC Establishment (VCE), which are combined with Traffic Enforcement Functions (TEFs) based on policing mechanisms and Cell Loss Control (CLC) scheme. By transient and stationary simulation approach for a single IWU and an IWU-CLS connection model, the most applicable method is indicated as a case study from view points of the communication quality, effective use of the bandwidth and processing load.

This paper describes the method of applying the integral form of Maxwell's equations to the transmission-line network used in the spatial network method for the modeling of curved conductor surfaces. The techniques of dealing with the transmission-line network near cylindrical conductor surface are explained in detail. To compare exact solutions with computed values, a cylindrical cavity resonator is analysed. The resonant frequencies and unloaded Q's for the computed three modes are obtained with the error of about 1%. Moreover, applying this treatment to the waveguide with magnetron anodeshape cross section, a cutoff-constant is computed successfully. It is found that the treatment proposed in this paper can be used as the method for modeling of curved conductor surface in the spatial network method. It is also considered that this treatment can be extend to TLM method.

The potential attenuation process of charged human body (HB) is analyzed. A two-dimensional circuit model is presented for predicting the potential attenuation characteristics of the HB charged on the floor. The theoretical equation for the HB potential is derived in the closed form in the Laplacian transformation domain, and the numerical inverse Laplace transform is used to compute it. The half-life or relaxation time of the HB potential for decay is numerically examined with respect to the electrical parameters of shoes. The experiment is also conducted for verifying the validity of the computed result.

The efficiency of a guided-probe fault location process is affected by the number of the probed lines. This number depends on the size of the target area and the method by which a line is selected for probing. This paper presents a method for reducing the size of the target area in a sequential circuit by introducing the concepts of Type- and Type- faults. This paper also presents a method of selecting lines for probing in a more efficient way. The efficiency of the proposed methods is demonstrated by experimental results.

In the modern hospital, the physical or chemical therapeutic procedure is regarded as paramount and psychological or spiritual care is quite frequently put aside. The goal of the Hyper Hospital" is to correct this. The Hyper Hospital is constructed in the computer based electronic network using an alternate reality system, such as the virtual reality system, as the human-machine-human interface. The nodes of the Hyper Hospital belong to a patient and also to a variety of medical care facilities; for example, the out patient office, the nursing care center, the medical examination unit, the operating theater, etc. The Hyper Hospital space consists of various kind of spaces including the alternate reality space owned and exclusively controlled by the patient himself or herself, and even the real space as well. Most of the physical contact, such as the visit to the out patient office by the patient, is actualized by the electronic connection of the patient private space and the public space of the hospital system. Prescription drugs, special care, and even the admission to the ward will be integrated into the distributed electronic network. To realize such a system, we need to solve many problems, such as the research on the network oriented architecture of the alternate reality, the development of human-machine interface particularly fitted to various disabilites, the study of the behavior of normal and diseased people, etc. The concept of the Hyper Hospital we are proposing is believed to be a new paradigm of the next generation of medical care.

In this letter an SR-latch circuit using Hopfield neural networks is introduced. An energy function suited for a neural SR-latch circuit is defined for which the global convergence is guaranteed. We also demonstrate how to compose master-slave (M/S) SR- and JK-flip flops of novel SR-latch circuits, and further an asynchronous binary counter of M/S JK-flip flops. Computer simulations are included to illustrate how each presented circuit operates.

This paper describes the circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for consumer video products, such as high-definition TV sets. Triple-stage conversion scheme combined with two new conversion methods, "Dynamic Sliding Reference Method" and "Triangular Interpolation Method," and an internal Bi-CMOS Sample/Hold circuit have been developed. These conversion methods require no adjustment circuit to fit reference voltages between conversion stages and realize small active area. As a result, a maximum conversion frequency of 16 MHz, acceptable SNRs of 56 dB and 48 dB for 10 kHz and 8 MHz input frequency respectively and small DNLE of 0.75 LSB have been achieved. This ADC is fabricated with 1.2 µm Bi-CMOS technology and integrates very small number of bipolar transistors of 2 K on a small active area of 2.52.7 mm2 and consumes 350 mW.

This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are fistly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.

A MOS VCO which has improved linearity of oscillation frequency versus control voltage and has no 1/2 divider is studied. The improved VCO characteristic has been obtained by the use of only two additional transistors, one of which has a role of a load and another of which has a role of a control current source in a differential type delay cell.

A particle trajectory estimation method from far electromagnetic fields are discussed in this paper. Authors have already presented a trajectory estimation method for single particle system and good agreements between a source particle trajectory and an estimated one have been obtained. For this, this paper discusses twin particles system as an examples of multi-particles systems for simplicity. First of all, it is pointed out that far electromagnetic fields from the twin particles system show quite different aspect from the single particle system using an example, radiation patterns produced by two particles which carry out circular motion. This result tells us that any trajectory estimations for general multi-particles system are almost impossible. However, it is shown that when the distance between the particles is small, the estimation method for the single particle system can be applied to the twin particles system, and that twin particles effects appear as disturbance of estimated trajectory.

A new algorithm, which is incorporated into the waveform relaxation analysis, for efficiently simulating the transient response of single lossy transmission lines or lossy coupled multiconductor transmission lines, terminated with arbitrary networks will be presented. This method exploits the inherent delay present in a transmission line for achieving simulation efficiency equivalent to obtaining converged waveforms with a single iteration by the conventional iterative waveform relaxation approach. To this end we propose 'line delay window partitioning' algorithm in which the simulation interval is divided into sequential windows of duration equal to the transmission line delay. This window scheme enables the computation of the reflected voltage waveforms accurately, ahead of simulation, in each window. It should be noted that the present window partitioning scheme is different from the existing window techniques which are aimed at exploiting the non–uniform convergence in different windows. In contrast, the present window technique is equivalent to achieving uniform convergence in all the windows with a single iteration. In addition our method eliminates the need to simulate the transmission line delay by the application of Branin's classical method of characteristics. Further, we describe a simple and efficient method to compute the attenuated waveforms using a particular form of lumped element model of attenuation function. Simulation examples of both single and coupled lines terminated with linear and nonlinear elements will be presented. Comparison indicates that the present method is several times faster than the previous waveform relaxation method and its accuracy is verified by the circuit simulator PSpice.

An emitter–coupled pair with a dynamic bias current and a source–coupled pair with a dynamic bias current are proposed as an exponential–law element and a square–law element that operate as a floating bipolar junction transistor (BJT) and a floating MOS field–effect transistor (MOSFET). In bipolar technology, a hyperbolic sine function circuit and a hyperbolic cosine function circuit are easily obtained by subtracting and summing the output currents of two symmetrical exponential–law elements with positive and negative input signals. In the same manner, an operational transconductance amplifier (OTA) and a squaring circuit are obtained by subtracting and summing the output currents of two symmetrical square-law elements with positive and negative input signals in CMOS technology. The proposed OTA and squaring circuit possess the widest input voltage range ever reported.

A new approach of data clustering which is capable of detecting linked or crossed clusters, is proposed. In conventional clustering approaches, it is a hard work to separate linked or crossed clusters if the cluster prototypes are difficult to be represented by a mathematical formula. In this paper, we extract the force information from data points using the concept of psychological potential field, and utilize the information to measure the similarity between data points. Through several experiments, the force shows its effectiveness in diiscriminating different clusters even if they are linked or corssed.

This paper describes a simple system of measuring the spatial distributions of spectral intensities with AgI-421 nm and AgI-546 nm among many optical spectrums emitted from an arc discharge between separating Ag contacts. In order to detect the intensities of two optical spectrums, the prototype equipment has two sets assembled with a CCD color linear image sensor, a lens and optical filters, which are arranged on rectangularity. The intensities of two spectrums can be recorded with 2 ms time-resolution within a long arc duration on a digital memory. The recorded digital signals are processed by using a personal computer in order to reconstruct two spatial distributions of spectral intensities in a cross section of arc column with the Algebraic Reconstruction Technique.

Gate-controlled negative differential resistance (NDR) due to interband tunneling has been observed at room temperature in a Surface Tunnel Transistor (STT). The STT consists of a highly degenerate p+-drain, an n+-doped channel with an insulated gate, and an n+-source connected to the channel. To demonstrate application as a functional device, a bistable circuit consisting of only one STT and one load resistor was organized and its operation was confirmed. The obtained valley current in the NDR characteristics of the STT, however, is relatively large and limits the device performance. In order to clarify the origin of the valley current, we fabricated p+-n+ tunnel diodes in which growth interruption was done at the pn junction, and investigated the dependence of the NDR characteristics on both the impurity concentration at the regrown interface and the temperature. These measurements indicate that the valley current is mainly caused by the excess tunneling current through traps formed by the residual oxygen at the regrown interface.

Kumar and Billinton have presented a new technique for obtaining the steady-state probabilities from a flow graph based on Markov model. By examining the graph and choosing suitable input and output nodes, the steady-state probabilities can be obtained directly by using the flow graph. In this paper this graphical technique is applied for a k-out-of-n: G repairable system. Consequently a new derivation way of the formulae for the steady-state availability and MTBF is obtained.

This paper proposes a dynamically randomized version of DES (called RDES) in which a input-dependent swapping Sk(X) is added onto the right half of the input in each round of DES. This new scheme decreases the probability of success in differential cryptanalysis because it decreases the characteristic probability. Each "best" two-round characteristic probability is analyzed for typical schemes of the RDES: (i) RDES-1 with a simple one-level swapping, (ii) RDES-1' with an optimal one-level swapping, (iii) RDES-2 with a simple two-level swapping, and (iv) RDES-2' with an optimal two-level swapping. The main results are as follows. (a) The differential attacks on the 16-round RDES-1' and the 16-round RDES-2 require more computational time than the exhaustive search. (b) A differential attack is substantially inapplicable to the 16-round RDES-2' because more than 263 chosen plaintext pairs are required. (c) The encryption/decryption speed of the n-round RDES is almost the same as that of the n-round DES.

This paper describes a new method to determine the 3-D position coordinates of a Lambertian surface from four shaded images acquired with an actively controlled, nearby moving point light source. The method treats both the case when the initial position of the light source is known and the case when it is unknown.

Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.