This paper describes a mobile information access system based on a multi-agent architecture. With the rapid progress of wireless data communications, mobile Internet access will be more and more popular. In mobile environments, user location plays an important role for information filtering and flexible communication service. In this paper, we propose a mobile information service system where a user with a handy terminal accesses Internet in an open air to look up map information and related town information. Each user information is managed by an independent agent process. And the agent provides each user with a personal service collaborating with other applications. A map-based information service example based on this architecture is also described.

In this paper, we propose a scalable service networking architecture as a TINA-like environment for providing flexibly various mobility services. The proposed architecture provides an environment that enables the advent of service providers and rapidly introduces multimedia applications, considering networks scalability. For supporting customized mobility services, this architecture adopts a new service component, which we call Omnipresent Personal Environment Manager (OpeMgr). In order to support mobile users who move between heterogeneous networks, for instance, between the TINA-like environment and the Internet environment, we propose a structure of a gateway. In addition, the proposed architecture uses the fixed and mobile agent approaches for supporting the user's mobility, and we evaluated their performances with comparing those approaches.

A novel CMOS half-wave rectifying transconductor is presented. The proposed circuit utilizes a simple new cascode current subtracter which is obtained from conventional cascode current mirror by a judicious reconfiguration to yield additional subtrahend signal path. The simulated DC transfer characteristics is highly linear with 1.1% linearity error up to 1.5V differential input voltage and the blunt corner at zero-crossing is 20mV. The output resistance is greater than 23MΩ and the total harmonic distortions at 100kHz with 1.5Vp-p in the positive half cycle are better than -46.5dB. The usable operating frequencies are up to 10MHz with maximum peak-to-peak input voltage and 75µW power consumption.

Our study investigated the realization of a high-precision MOS current-mode circuit. Simple studies have implied that it is difficult to achieve a high signal-to-noise ratio (S/N) in a current-mode circuit. Since the signal voltage at the internal node is suppressed, the circuit is sensitive to various noise sources. To investigate this, we designed and fabricated a current-mode sample-and-hold circuit with a 3V power supply and a 20MHz clock speed, using a standard CMOS 0.6µm device process. The measured S/N reached 57dB and 59dB in sample mode, and 51dB and 54dB in sample-and-hold mode, with 115µA from a 3V power supply and 220µA from a 5V power supply of input currents and a 10MHz noise bandwidth. The S/N analysis based on an actual circuit was done taking device noise sources and the fold-over phenomena of noise in a sampled system into account. The calculation showed 66.9dB of S/N in sample mode and 59.5dB in sample-and-hold-mode with 115µA of input current. Both the analysis and measurement indicated that 60dB of S/N in sample mode with a 10MHz noise bandwidth is an achievable value for this sample-and-hold circuit. It was clear that the current-mode approach limits the S/N performance because of the voltage suppression method. This point should be further studied and discussed.

A non-isothermal device simulation, consisting of solving heat flow equation three-dimensionally together with other semiconductor equations two-dimensionally, is reported for various arrangements of a pluralty of transistors mounted on a single chip. These arrangements are intended to simulate the real situation in an IC chip whereas a three-dimensional solution of the heat flow equation is aimed at accurately determining the thermal interdependence among individual transistors. As a result, the drain current versus drain voltage characteristics of a miniaturized transistor is found to exhibit a heat-induced negative resistance region.

We present theoretical results on the convergence of iterative methods for the solution of linear differential-algebraic equations arising form circuit simulation. The iterative methods considered include the continuous-time and discretetime waveform relaxation methods and the Krylov subspace methods in function space. The waveform generalized minimal residual method for solving linear differential-algebraic equations in function space is developed, which is one of the waveform Krylov subspace methods. Some new criteria for convergence of these iterative methods are derived. Examples are given to verify the convergence conditions.

Nonuniform transmission lines are crucial in integrated circuits and printed circuit boards, because these circuits have complex geometries and layout between the multi layers, and most of the transmission lines possess nonuniform characteristics. In this article, an efficient numerical method for analyzing nonuniform transmission lines has been presented by using the Chebyshev expansion method and moment techniques. Efficiency on computational cost is demonstrated by numerical example.

A CAD-based faulty portion diagnosis technique for CMOS-LSI with single fault using abnormal Iddq has been developed to indicate the presence of physical damage in a circuit. This method of progressively reducing the faulty portion, works by extracting the inner logic state of each block from logic simulation, and by deriving test vector numbers with abnomal Iddq. To easily perform fault diagnosis, the hierarchical circuit structure is divided into primitive blocks including simple logic gates. The diagnosis technique employs the comparative operation of each primitive block to determine whether one and the same inner logic state with abnormal Iddq exists in the inner logic state with normal Iddq or not. The former block is regarded as normal block and the latter block is regarded as faulty block. Faulty portion of the faulty block can be localized easily by using input logic state simulation. Experimental results on real faulty LSI with 100k gates demonstrated rapid diagnosis times of within ten hours and reliable extraction of the faulty portion.

We propose a top-down approach for cosimulation of hardware/software co-designs for embedded systems and introduce a component logical bus architecture as an interface between software components implemented by processors and hardware components implemented by custom logic circuits. Co-simulation using a component logical bus architecture is possible is the same environment from the stage at which the processor is not yet finalized to the stage at which the processor is modeled in register transfer language. Models based upon a component logical bus architecture can be circulated and reused. We further describe experimental results of our approach.

Recently, two new efficient server-aided RSA secret computation protocols were proposed. They are efficient and can guard against some active attacks. In this letter, we propose two multi-round active attacks which can effectively reduce their security level even break them.

Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.

In this paper, we present CB-Power, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.

In this paper, we propose an efficient solution for the Multiple Constant Multiplication (MCM) problem. The method uses hierarchical clustering to exploit common subexpressions among constants and reduces the number of shifts, additions, and subtractions. The algorithm defines appropriate weights, which indicate operation priority, and selects common subexpressions, resulting in a minimum number of local operations. It can also be extended to various high-level synthesis tasks such as arbitrary linear transforms. Experimental results for several error-correcting codes, digital filters and Discrete Cosine Transforms (DCTs) have shown the effectiveness of our method.

The analysis of an architecture may provide statistic information on the use of the resources and on the execution time. Some of these information need just a static analysis. Others, such as the execution time, may need dynamic analysis. Moreover as the computation time of behavioral descriptions (control step time unit) and RTL ones (cycle based) may differ a lot, unexpected architectures may be generated by behavioral synthesis. Therefore means to debug the results of behavioral synthesis are required. This paper introduces a new approach to integrate an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. The simulator and the behavioral synthesis are based on the same model. This model allows to link the behavioral description and the architecture produced by synthesis. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. It may also be used to debug the behavioral specification.

The FPGA logic synthesis consists of logic minimization step and technology mapping step. These two steps are usually performed separately to reduce the complexity of the problem. Conventional logic minimization methods try to minimize the number of literals of a given Boolean network, while FPGA technology mapping techniques attempt to minimize the number of basic blocks. However, minimizing the number of literals, which is target architecture-independent feature, does not always lead to minimization of basic block count, which is a FPGA architecture specific feature. Therefore, most of the existing technology mapping systems take into account reorganization of its input circuits to get better mapping results. Such a loosely coupled logic synthesis paradigm may cause difficulties in finding the optimal solution. In this paper, we propose a new logic synthesis approach where logic minimization and technology mapping steps are performed tightly coupled. Our system takes into account FPGA specific features in logic minimization step and thus our technology mapping step does not need to resynthesize the Boolean network. We formulate the technology mapping problem as a graph covering problem. Such formulation provides more global view to optimality and supports versatile cost functions. in addition, a fast and exact library management technique is devised for efficient FPGA cell matching which is one of the most frequently used operations in the FPGA logic synthesis.

High-Tc SQUID was applied to the detection of magnetized fine particle moving at high speed. Two types of SQUIDs were used. One was a large washer type and the other was a flux transformer type. Their Josephson junctions were step edge type. The iron particle was attached on a nylon wire and scanned under the SQUID. High-Tc SQUID detected an iron particle of 50 µm diameter running at 800 m/min. It was shown that the magnetic field measured by the SQUID was proportional to the volumer of the particle and is inversely proportional to the distance between the SQUID and the particle. This technique using high-Tc SQUID is hopeful not only to wire production line but also for the processing of food and medicine, etc.

We report on progress in the development of high-current-density all-NbN tunnel junctions for application as submillimeter wave SIS mixers. A very high current density up to 54 kA/cm2, roughly an order of magnitude larger than any reported results for all-NbN tunnel junctions, was achieved in the junctions with a thin aluminum nitride (AIN) tunnel barrier. Even though the junctions have a very high current density, they showed high-quality junction characteristics with a large gap voltage, sharp quasipartical current rise, and small subgap leakage current. The junctions also exhibited good Josephson tunneling behavior, excellent terahertz response, and sensitive heterodyne mixing properties. NbN/AIN/NbN tunnel junctions were integrated with a NbN thin-film antenna to investigate the terahertz responses and the heterodyne mixing properties in a quasioptical mixer testing system. Photon-assisted tunneling steps were clearly observed on the I-V curve with irradiation up to 1 THz, and low-noise heterodyne mixing was demonstrated in the 300-GHz band.

This study shows the results of evaluating the flux noises at low frequency when the alternating current(AC) bias direct offset integrated technique(DOIT) with additional positive feedback (APF) is used in a high-Tc dc superconducting quantum interference device (SQUID). The AC-bias DOIT can reduce low-frequency noise without increasing the level of white noise because each operating point in the two voltage-flux characteristics with AC bias can always be optimum on the magnetometer in the high-Tc dc-SQUID. APF can improve the effective flux-to-voltage transfer function so that it can reduce the equivalent flux noise due to the voltage noise of the preamplifier in the magnetometer. The use of APF combined with the AC-bias DOIT reduced the noise of the magnetometer by factors of 1.5 (33µΦ0/Hz vs. 50 µΦ0/Hz) at100 Hz, 3.5 (43 µΦ0/Hz vs. 150 µΦ0/Hz) at 10 Hz, and 5.2 (67 µΦ0/Hz vs. 351 µΦ0/Hz) at 1 Hz as compared with the noise levels that were obtained with the static-current-bias DOIT. The contribution of the factors at 1 Hz is about 2 by APF and 2.6 by AC bias. The performance of improving the flux noise in the AC -bias DOIT with APF is almost equal to that of the flux locked loop (FLL) circuits in which the flux modulation uses a coupling system with a transformer and with the AC bias.

New THz radiation devices made of high-Tc superconductors are fabricated and their characteristics are studied in detail. Ultrashort electromagnetic pulses with 0.5 ps width have been radiated into free space from current biased devices made of superconducting YBa2Cu3O7 (YBCO) films by exciting with femtosecond laser pulses. The Fourier spectrum of them extends up to 3 THz. The radiation mechanism is ascribed to the ultrafast supercurrent modulation by the optical pulses. The THz waveform is analyzed using rate equations describing the relaxation of photoexcited quasiparticles. By the improvement of the device structure and the collecting optics, the radiation power can be increased up to 0.5 µW. A new type THz radiation from YBCO films under an external magnetic field without a transport current is also reported.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.