A self-learning analog neural network LSI with non-volatile analog memory which can be updated with more than 13-bit resolution has been designed, fabricated and tasted for the first time. The non-volatile memory is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance. We also propose a partially-serial weight-update architecture in which the plural synapse circuits use a weight-update circuit in common to reduce the circuit area. A prototype chip fabricated using a 1.3-µm double-poly CMOS process includes 50 synapse elements and its computational power is 10 MCPS. The weights can be updated at a rate of up to 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.

In this paper, we propose a quasi-optimum multiuser detector using co-channel interference cancellation technique in an asynchronous code-division multiple-access communication system, and evaluate its performance by computer simulations. In the proposed detector, maximum likelihood sequence estimation is performed to compare the original received signal with replicas of the signal which are produced from the demodulation data bit sequence of a co-channel interference canceller. In several conditions, the proposed detector is compared with the co-channel interference canceller, and it is shown that the average bit error rate characteristics of the propose detector are improved considerably.

In this study, we show how changing a frequency in one of N chaotic circuits coupled by a resistor effects our system by means of both circuit experiment and computer calculation. In these N chaotic circuits, N-1 circuits are completely identical, and the remaining one has altered the value of the oscillation frequency. It is found that for the case of N = 3 when a value of a coupling resistor is gradually increased, only one circuit with different frequency exhibits bifurcation phenomena including inverse period-doubling bifurcation, and for larger value of coupling resistor, the chaotic circuit with different frequency suddenly stops oscillating and the remaining two chaotic circuits exhibit completely anti-phase synchronization.

This study was conducted to assess the relationship between fatigue and pupillary responses. Pupillary responses, ECG and blood pressure were measured for 24 hours every 30 min in 8 subjects. A questionnaire was used to rate subjective feeling of fatigue. Twenty-four hours were divided equally into four 6-hour blocks. Subjective feeling of fatigue increased markedly in the fourth block, and the difference in subjective fatigue between fourth and first blocks was significant. Of nine pupillary responses, the pupil diameter was found to decrease with time. With respect to the function of the autonomic nervous system such as heart rate, systolic blood pressure and diastolic blood pressure, only heart rate was found to be sensitive to the increased subjective feeling of fatigue. A significant difference was found in the mean pupil diameter and mean heart rate between the last and first blocks. This result indicates that pupil diameter is related to fatigue and can be used to assess fatigue. Possible implications for fatigue assessment are discussed.

We have constructed a new concept device with combination of ferroelectric and ferromagnetic materials by a laser ablation technique. An ideal hetero-epitaxy can be obtained owing to the similar crystal structure of perovskite type ferroelectric Pb (Zr, Ti) O3; (so called PZT) and ferromagnetic (La, Sr) MnO3. The ferromagnetic (La, Sr) MnO3 compounds are well known for their colossal magnetoresistance (CMR) properties. The CMR effect is strongly affected by the lattice stress. The PZT, on the other hand, is famous for its large piezoelectrics. We can introduce the lattice stress easily by applying voltage for the piezoelectric compounds. In the heterostructured ferromagnetic/ferroelectric devices, there are remarkable interesting phenomena. Electric properties of the ferromagnetic material can be controlled by piezoelectric effect via distortion of crystal structure.

We propose an interactive identification scheme based on the quadratic residue problem. Prover's identity can be proved without revealing his secret information with only one accreditation. The proposed scheme requires few computations in the verification process, and a small amount of memory to store the secret information, A digital signature based on this scheme is proposed, and its validity is then proved. Lastly, analysis about the proposed scheme is presented at the end of the paper.

It is highly desirable to develop an efficient and flexible dynamic channel assignment algorithm in order to realize an integrated traffic TDMA mobile radio communication network. In this paper, an integrated traffic TDMA system is studied in which transmission of voice and data are assumed to occupy one and n time slots in each TDMA frame, respectively. In general, there are two types of channel (time slot) assignment algorithms: the partitioning algorithm and the sharing algorithm. However, they are not well-suited to the multimedia traffic consisting of various information sources that occupy different number of slots per frame. In this paper, assuming that voice is much more sensitive to transmission delay than data, an algorithm based on the sharing algorithm with flexible tima slot management scheme is proposed. Our method tries to vary the number of data slots adaptively so as to improve the quality of servive of voice calls and the system capacity. Computer simulations show the good performance of the proposed algorithm when compared to conventional channel assignment algorithms.

We propose a new bit timing recovery (BTR) scheme, what we call Step Sampled BTR (SSBTR), that can lower the sampling clock frequency and shorten the clock phase convergence time, for burst signals in high bit rate wireless access systems. The SSBTR scheme has the following characteristics. A sine wave resulting from the BTR code passing through a Nyquist Transmission System is always used, the sampling clock has a lower frequency than the system clock, and the clock phase of Intermediate Frequency (IF) signal input can be estimated from as few as 3 sampled data. The SSBTR scheme corrects the clock phase only once in a burst signal. Therefore, in some wireless access systems, some kind of operation must be performed after the SSBTR, in order to deal with long burst signals, instability of the system clock, and so on. In other wireless access systems that do not have these problems, clock phase can be fixed by the SSBTR scheme alone. The preformance of the SSBTR scheme with respect to additive white Gaussian noise (AWGN) was examined by computer simulation. In addition, when SSBTR is implemented in hardware, there are imperfections in the circuitry that lead to phase estimation error and thus deterioration, so we studied the effects of several such imperfections by computer simulation. The results of these simulations clarify the performance of the SSBTR scheme.

SOI (Silicon On Insulator) transistors have certain problems due to the floating body. These problems become remarkable in the memory cell transistors of DRAMs. We propose a new refresh function and circuits for SOI DRAMs. And we obtained the result that this refresh function removed the injected hole from the body region and gave stable body potential by the device simulation. Therefore we can realize the long data retention characteristics for SOI DRAMs without an increase of the memory cell area or an additional refresh operation.

This paper presents an adaptive coding rate trellis-coded octal phase-shift keying system with rates of 1/3, 1/2, 2/3, and 5/6, under the restriction of a constant transmission bit rate, where the ratio between the informaion bits and error-correcting redundant bits varies according to channel conditions. This system has the advantage of using a simple modem configuration. Because it has no need to change modulation type, transmitter/receiver filters, and clock and carrier recovery circuits, and it can use a convenient Read-Only-Memory table encoder. As for code design, the trellis structures and its signal assignments for rates of 1/3, 1/2, and 5/6 are proposed and investigated, and their BER performances are estimated. As a result, when the system requirement is to keep the bit error rate of 10-4, this system can operate at the lower Eb/No value of 1.5dB on the reduction of transmitting information bits.

This paper provides an architectural study of optical multiple-ring trunk-transmission networks using high-speed Time Division Multiplexing (TDM), and proposes two algorithms for distributed control environments. We propose a path-setup algorithm that uses Token protocol over Section Overhead (SOH) bytes, by which network-nodes communicate with each other to reserve bandwidth. A classified path restoration algorithm is also proposed that offers 3 path classes in terms of restoration performance. Class A paths, the most reliable, never lose any bit even against unpredictable disasters. They are realized by path-duplication at the source node, route diversity,and hitless switching at the destination node. Class B paths are restored by re-routing, where the original path-setup algorithm is reused. Class C paths are the most economical because a failed path is restored by maintenance action.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

This paper describes a neuro-based optimization algorithm for three dimensional (3-D) cylindric puzzles which are problems to arrange the irregular-shaped slices so that they perfectly fit into a fixed three dimensional cylindric shape. First, the idea to expand the 2-dimensional tiling technique to 3-dimensional puzzles is described. Next, to energy function with the fitting function of each polyomino is introduced, which is available for 3-D cylindric puzzles. Furthermore our algorithm is applied to several examples using the analog neural array. Finally, it is shown that our algorithm is useful for solving 3-D cylindric puzzles.

From a sequence {ai}i0 over GF(p) with period pn-1 we can obtain another periodic sequence {i}i0 with period pn-2 by deleting one symbol at the end of each period. We will give the bounds (upper bound and lower bound) of linear complexity of {i}i0 as a typical example of instability of linear complexity. Derivation of the bounds are performed by using the relation of characteristic polynomials between {ai}i0 and {ai(j)}i0={ai+j}i0, jGF(p){0}. For a binary m-sequence {ai}i0 with period 2n-1, n-1 a prime, we will give the explicit formula for the characteristic polynomial of {i}i0.

A noble blind equalization algorithm (BEA) using a single/multilevel modulus is proposed. According to the residual intersymbol interference (ISI) level of the equalizer output, the new algorithm adopts relevantly a single modulus or a multilevel modulus to form its cost function. Moreover, since the proposed approach separates complex two-dimensional signal into in-phase and quadrature components, and forms the error signals for each component, it has inherently the capability of phase recovery. Hence, it improves the performances of steady-state and recovers the phase rotation without any degradation of transient property. Simulation results confirm the effectiveness of the new approach.

A small-sized three-stage GaAs power module has been developed for portable digital radios using M-16QAM modulation. This module has exhibited typical P1dB of 10 W with PAE of 48% and a power gain of 35 dB at a low supply voltage of 6.5 V in 1.453-1.477 GHz band. The volume of the module is only 1.5 cc, which is one of the smallest value in 10 W class modules ever reported. In order to realize the reduced size and the high power performances simultaneously, the module has employed new power divider/combiner circuits with significant features of the reduced occupation area, the improved isolation properties and the function of second-harmonic control.

In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.

An advanced intelligent network (IN) provides service management along with telecommunication services, and has a two-layer architecture, i.e., a transmission layer and an intelligent layer. An advanced IN's programmability is achieved by a service-independent platform of nodes in the intelligent layer, and service-dependent software called logic programs. In contrast to telecommunication services, models for service management have not yet been established. This paper presents both execution and specification models for service management. The execution model is composed of three hierarchies that apply to various kinds of management operation. The specification model has the capability to define the details of data items. The specification language for service management is also proposed. Simulation on dynamic SQL based DBMS solved that; (1) Logic programs for service management can be made small size on the model, and (2) To provide efficient database operation, programmability must be enhanced if service management includes table with variable number of field operation.