Nonuniform transmission lines are crucial in integrated circuits and printed circuit boards, because these circuits have complex geometries and layout between the multi layers, and most of the transmission lines possess nonuniform characteristics. In this article, an efficient numerical method for analyzing nonuniform transmission lines has been presented by using the Chebyshev expansion method and moment techniques. Efficiency on computational cost is demonstrated by numerical example.

A novel CMOS half-wave rectifying transconductor is presented. The proposed circuit utilizes a simple new cascode current subtracter which is obtained from conventional cascode current mirror by a judicious reconfiguration to yield additional subtrahend signal path. The simulated DC transfer characteristics is highly linear with 1.1% linearity error up to 1.5V differential input voltage and the blunt corner at zero-crossing is 20mV. The output resistance is greater than 23MΩ and the total harmonic distortions at 100kHz with 1.5Vp-p in the positive half cycle are better than -46.5dB. The usable operating frequencies are up to 10MHz with maximum peak-to-peak input voltage and 75µW power consumption.

Our study investigated the realization of a high-precision MOS current-mode circuit. Simple studies have implied that it is difficult to achieve a high signal-to-noise ratio (S/N) in a current-mode circuit. Since the signal voltage at the internal node is suppressed, the circuit is sensitive to various noise sources. To investigate this, we designed and fabricated a current-mode sample-and-hold circuit with a 3V power supply and a 20MHz clock speed, using a standard CMOS 0.6µm device process. The measured S/N reached 57dB and 59dB in sample mode, and 51dB and 54dB in sample-and-hold mode, with 115µA from a 3V power supply and 220µA from a 5V power supply of input currents and a 10MHz noise bandwidth. The S/N analysis based on an actual circuit was done taking device noise sources and the fold-over phenomena of noise in a sampled system into account. The calculation showed 66.9dB of S/N in sample mode and 59.5dB in sample-and-hold-mode with 115µA of input current. Both the analysis and measurement indicated that 60dB of S/N in sample mode with a 10MHz noise bandwidth is an achievable value for this sample-and-hold circuit. It was clear that the current-mode approach limits the S/N performance because of the voltage suppression method. This point should be further studied and discussed.

This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.

A non-isothermal device simulation, consisting of solving heat flow equation three-dimensionally together with other semiconductor equations two-dimensionally, is reported for various arrangements of a pluralty of transistors mounted on a single chip. These arrangements are intended to simulate the real situation in an IC chip whereas a three-dimensional solution of the heat flow equation is aimed at accurately determining the thermal interdependence among individual transistors. As a result, the drain current versus drain voltage characteristics of a miniaturized transistor is found to exhibit a heat-induced negative resistance region.

We present theoretical results on the convergence of iterative methods for the solution of linear differential-algebraic equations arising form circuit simulation. The iterative methods considered include the continuous-time and discretetime waveform relaxation methods and the Krylov subspace methods in function space. The waveform generalized minimal residual method for solving linear differential-algebraic equations in function space is developed, which is one of the waveform Krylov subspace methods. Some new criteria for convergence of these iterative methods are derived. Examples are given to verify the convergence conditions.

A CAD-based faulty portion diagnosis technique for CMOS-LSI with single fault using abnormal Iddq has been developed to indicate the presence of physical damage in a circuit. This method of progressively reducing the faulty portion, works by extracting the inner logic state of each block from logic simulation, and by deriving test vector numbers with abnomal Iddq. To easily perform fault diagnosis, the hierarchical circuit structure is divided into primitive blocks including simple logic gates. The diagnosis technique employs the comparative operation of each primitive block to determine whether one and the same inner logic state with abnormal Iddq exists in the inner logic state with normal Iddq or not. The former block is regarded as normal block and the latter block is regarded as faulty block. Faulty portion of the faulty block can be localized easily by using input logic state simulation. Experimental results on real faulty LSI with 100k gates demonstrated rapid diagnosis times of within ten hours and reliable extraction of the faulty portion.

We propose a top-down approach for cosimulation of hardware/software co-designs for embedded systems and introduce a component logical bus architecture as an interface between software components implemented by processors and hardware components implemented by custom logic circuits. Co-simulation using a component logical bus architecture is possible is the same environment from the stage at which the processor is not yet finalized to the stage at which the processor is modeled in register transfer language. Models based upon a component logical bus architecture can be circulated and reused. We further describe experimental results of our approach.

Recently, two new efficient server-aided RSA secret computation protocols were proposed. They are efficient and can guard against some active attacks. In this letter, we propose two multi-round active attacks which can effectively reduce their security level even break them.

Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT) -based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches.

In this paper, we present CB-Power, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.

In this paper, we propose an efficient solution for the Multiple Constant Multiplication (MCM) problem. The method uses hierarchical clustering to exploit common subexpressions among constants and reduces the number of shifts, additions, and subtractions. The algorithm defines appropriate weights, which indicate operation priority, and selects common subexpressions, resulting in a minimum number of local operations. It can also be extended to various high-level synthesis tasks such as arbitrary linear transforms. Experimental results for several error-correcting codes, digital filters and Discrete Cosine Transforms (DCTs) have shown the effectiveness of our method.

The analysis of an architecture may provide statistic information on the use of the resources and on the execution time. Some of these information need just a static analysis. Others, such as the execution time, may need dynamic analysis. Moreover as the computation time of behavioral descriptions (control step time unit) and RTL ones (cycle based) may differ a lot, unexpected architectures may be generated by behavioral synthesis. Therefore means to debug the results of behavioral synthesis are required. This paper introduces a new approach to integrate an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. The simulator and the behavioral synthesis are based on the same model. This model allows to link the behavioral description and the architecture produced by synthesis. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. It may also be used to debug the behavioral specification.

The FPGA logic synthesis consists of logic minimization step and technology mapping step. These two steps are usually performed separately to reduce the complexity of the problem. Conventional logic minimization methods try to minimize the number of literals of a given Boolean network, while FPGA technology mapping techniques attempt to minimize the number of basic blocks. However, minimizing the number of literals, which is target architecture-independent feature, does not always lead to minimization of basic block count, which is a FPGA architecture specific feature. Therefore, most of the existing technology mapping systems take into account reorganization of its input circuits to get better mapping results. Such a loosely coupled logic synthesis paradigm may cause difficulties in finding the optimal solution. In this paper, we propose a new logic synthesis approach where logic minimization and technology mapping steps are performed tightly coupled. Our system takes into account FPGA specific features in logic minimization step and thus our technology mapping step does not need to resynthesize the Boolean network. We formulate the technology mapping problem as a graph covering problem. Such formulation provides more global view to optimality and supports versatile cost functions. in addition, a fast and exact library management technique is devised for efficient FPGA cell matching which is one of the most frequently used operations in the FPGA logic synthesis.

In this paper, we propose a scalable service networking architecture as a TINA-like environment for providing flexibly various mobility services. The proposed architecture provides an environment that enables the advent of service providers and rapidly introduces multimedia applications, considering networks scalability. For supporting customized mobility services, this architecture adopts a new service component, which we call Omnipresent Personal Environment Manager (OpeMgr). In order to support mobile users who move between heterogeneous networks, for instance, between the TINA-like environment and the Internet environment, we propose a structure of a gateway. In addition, the proposed architecture uses the fixed and mobile agent approaches for supporting the user's mobility, and we evaluated their performances with comparing those approaches.

This paper describes a mobile information access system based on a multi-agent architecture. With the rapid progress of wireless data communications, mobile Internet access will be more and more popular. In mobile environments, user location plays an important role for information filtering and flexible communication service. In this paper, we propose a mobile information service system where a user with a handy terminal accesses Internet in an open air to look up map information and related town information. Each user information is managed by an independent agent process. And the agent provides each user with a personal service collaborating with other applications. A map-based information service example based on this architecture is also described.

Satellite beam-switching problems are studied where there are m up-link beams, n down-link beams and multiple carriers per beam. By augmenting a traffic matrix with an extra row and column, it is possible to find a sequence of switching modes ((0,1)-matrices with genrally multiple unit entries in each row and column) that realize optimal transmission time. Switching modes generated are shown to be linearly independent. The number of switching modes required for an mn matrix is bounded by (m1)(n1)1. For an augmented (m1)(n1) matrix, the bound is then mn1. The bounds on the number of switching modes and the computational complexity for a number of related satellite transmission scheduling problems are lowered. In simplified form, the results (particularly the linear independence of permutation matrices generated) apply to algorithmic decomposition of doubly stochastic matrices into convex combinations of permutation matrices.

We investigate performance of TCP protocol over ATM networks by using a simulation technique. As the ATM layer, we consider (1) rate-based control of the ABR service class and (2) an EPD (Early Packet Discard) technique applied to the UBR service class and (3) and EPD with per-VC accounting for fairness enhancement applied to the UBR service class. In comparison, we adopt a multi-hop network model where the multiple ATM switches are interconnected. In such a network, unfairness among connections is a possible cause of the problem due to differences of the number of hops and/or the round trip times among connections. Simulation results show that the rate-based control method of ABR achieves highest throughput and best fairness in most circumstances. However, the performance of TCP over ABR is degraded once the cell loss takes place due to the inappropriate control parameter setting. To avoid this performance degradation, we investigate the appropriate parameter set suitable to TCP on ABR service. As a result, parameter tuning can improve the performance of TCP over ABR, but limited. We therefore consider TCP over ABR with EPD enhancement where the EPD technique is incorporated into ABR. We last consider the multimedia network environment, where the VBR traffic exists in the network in addition to the ABR/UBR traffic. By this, we investigate an applicability of the above observations to a more generic model. Through simulation experiments, we find that the similar results can be obtained, but it is also shown that parameters of the rate-based congestion control must be chosen carefully by taking into account the existence of VBR traffic. For this, we discuss the method to determine the appropriate control parameters.

A Unique Input/Output (UIO) sequence for the state J of a protocol is a sequence of input/output pairs that is unique to state J. Obtaining UIO sequences from the protocol specification is a very important problem in protocol conformance testing. Let n and m be the total number of states and transitions of the protocol, respectively, and dmax be the largest outdegree of any state, W. Chun and P. D. Amer proposed an O(n2(dmax)2n-1) algorithm to obtain the minimum-length UIO sequences (where the length refers to the number of input/output pairs). However, n and m are normally very large for real protocols. In this paper, we propose an O(n*m) algorithm for obtaining UIO sequences. In theory, our algorithm yields a UIO sequence which contains at most n1 input/output pairs. In experimentation, ten protocol examples collected from recent papers, the ISO TP0 protocol, the ISDN Q. 931 network-side protocol, and the CCITT X. 25 protocol show that in average the obtained UIO sequences are only 11.8% longer than the minimum-length ones, and 97.4% of the existent UIO sequences can be found. And our algorithm is extended for minimizing the cost of UIO sequences and for obtaining synchronizable UIO sequences, which have not been achieved by any algorithm proposed earlier.

In this paper we analyze the properties of regular segmentation schemes for 2-D Field Programmable Gate Arrays (FPGAs). Such schemes can be viewed as generalization of the Xilinx-like wire segmentations. We discuss their routing properties and propose a new FPGA design concept of applying architectural coupling to improve chip routability. We give the experimental routing results of such architectures for justification.