A neural network approach called the "Gradual Neural Network (GNN)" for the time slot assignment problem in the TDM multicast switching system is presented in this paper. The goal of this NP-complete problem is to find an assignment of packet transmission requests into a minimum number of time slots. A packet can be transmitted from one source to several destinations simultaneously by its replication. A time slot represents a switching configuration of the system with unit time for each packet transmission through an I/O line. The GNN consists of the binary neural network and the gradual expansion scheme. The binary neural network satisfies the constraints imposed on the system by solving the motion equation, whereas the gradual expansion scheme minimizes the number of required time slots by gradually expanding activated neurons. The performance is evaluated through simulations in practical size systems, where the GNN finds far better solutions than the best existing altorithm.

In this paper, the error performance of block coded 8-PSK modulation systems of length 32, designed for unequal error protection (UEP) of messages transmitted over a Rayleigh fading channel, is investigated. Computer simulation are reported showing that, with transmission over a Rayleigh fading channel, a good improvement in coding gain is obtained by the use of a binary linear UEP (LUEP) code as a constituent code in the multilevel construction, compared with conventional block coded modulation (BCM) of the same length.

Our compact switching converter using a thin-film microtransformer mono-lithically integrated with rectifier diodes represents the first step in developing a monolithic micro-switching converter that can be integrated with semiconductor devices and magnetic components. This converter is a single-ended forward converter with resonant reset and operates successfully at 15 MHz. The maximum output power is 0.5 W.

We present a high performance AlGaAs/GaAs power HBT with very low thermal resistance for digital cellular phones. Device structure with emitter air-bridge is utilized and device layout is optimized to reduce thermal resistance based on three-dimensional thermal flow analysis, and in spite of a rather thick substrate (100 µm), which achieved a low thermal resistance of 23/W for a multi-finger (440 µm240 fingers) HBT. This 40 finger HBT achieved power added efficiency (PAE) of over 53%, 29.1 dBm output power (Pout) and high associated gain (Ga) of 13.5 dB with 50 kHz adjacent channel leakage power (Padj) of less than -48 dBc under a 948 MHz π/4-shifted QPSK modulation with 3.4 V emitter-collector voltage. We also investigated the difference of RF performance between two bias modes (constant base voltage and current), and found which mode is adequate for each stage in several stage power amplifier for the first time.

Characteristics of a distortion, gain and efficiency of a power amplifier grow worse extremely by different phases of the load reflection coefficient when load impedances of the power amplifier are far from 50 Ω. It was found that the value of the distortion, gain and efficiency showed the tradeoff behavior when the phase of the reflection coefficient was different in 180 degrees. Therefore we have proposed new two- and four-parallel unit power amplifiers combined in 90 degree and 45 degree different phases each in order to accomplish low distortion and high efficiency in wide range of load impedances without an isolator. We studied the power amplifiers by simulation based on experiments and realized an amplifier in that adjacent channel leakage power of π/4-DQPSK modulation (for Japan's digital cellular system) is less than -45 dBc and efficiency is over 45% in range of load VSWR less than 3.

An analysis method is proposed for nonstationary waveforms. Modelling of a nonstationary waveform is first given in this paper. A waveform is represented by multiple oscillations. The instantaneous phase angle of each oscillation is written by three terms, predictive component, residual component, and initial phase constant. By this modelling, waveform analysis results in estimations of frequency, calculation of residual pbase in instantaneous phase angle. The Instantaneous Maximum Entropy Methods (IMEN) is utilized for frequency estimation. The residual phase angle is obtained by the Vandermonde matrix and the condition of continuity of phase angle among n-neighbourhood. Another analysis method is also proposed by the normalization of waveform parameters. The evaluation of the proposed method is done using artificially composed waveform signals. Novel and useful knowledge was provided by this analysis.

This paper presents the several bifurcation phenomena of harmonic oscillations occurred in nonlinear three-phase circuit. The circuit consists of delta-connected nonlinear inductors, capacitors and three-phase symmetrical voltage sources. We analyze the bifurcations of the oscillations by the homotopy method. Additionally, we confirm the bifurcation phenomena by real experiments. Furthermore, we reveal the effect of nonlinear couplings of inductors by the comparison of harmonic oscillations in a single-phase circuit.

In this paper a cyclic place-timed controlled marked graph (PTCMG), which is an extended class of a cyclic controlled marked graph (CMG), is presented as a model of discrete event systems (DESs). In a PTCMG, time constraints are attached to places instead of transitions. The time required for a marked place to be marked again is represented in terms of time constraints attached to places. The times required for an unmarked place to be marked under various controls, are calculated. The necessary and sufficient condition for a current marking to be in the admissible marking set with respect to the given forbidden condition is provided, as is the necessary and sufficient condition for a current marking to be out of the admissible marking set with respect to the forbidden condition in one transition. A maximally permissive state feedback control is synthesized in a PTCMG to guarantee a larger admissible marking set than a CMG for most forbidden state problems. Practical applications are illustrated for a railroad crossing problem and an automated guided vehicle (AGV) coordination problem in a flexible manufacturing facility.

Electric fishes generate an AC electric field around themselves by the electric organ in the tail. Spatial distortion of the field by nearby objects is detected by an electroreceptor array located an over the body surface to localize the object electrically when other senses such as vision and mechanosense are useless. Each fish has its own 'frequency band' for its electric organ discharges, and jamming of the electrolocation system occurs when two fish with similar discharge frequencies encounter. To avoid janmming, the fish shift their discharge frequencies in appropriate directions. A computational algorithm for this electrical behavior and its neuronal implementation by the brain have been discovered. The design features of the system, however, are rather complex for this simple behavior and cannot be readily explained by functional optimization processes during evolution. To gain insights into the origin of the design features, two independently evolved electric fish species which perform the same behavior are compared. Complex features of the neuronal computation may be explained by the evolutionary history of neuronal elements.

Scattering of a plane electromagnetic wave by a conducting wedge will be discussed. The former solution can not be applicable to all the transition regions when its parameter is constant. This study shows a new solution which consists of only one expression applicable to the shadow region, the illuminated region and the transition regions, and which has no parameter.

This paper proposes the Snow Crystal method, which aims to present the hierarchies of a large-scale telecommunication network on one screen. This will improve the user interface of a network operation system for network operations and management. With the proposed presentation method, locations of nodes are automatically set based on the number of hierarchy levels and the number of nodes. The nodes in the same hierarchy level are located on the same circle at even intervals. The center of the circle that corresponds to the top hierarchy level is set at the center of the screen. The radius of the circle is determined by the number of nodes. The centers of circles that correspond to the second hierarchy levels belonging to the nodes of the top hierarchy level, are located on a larger circle with the same center point as the top level circle at even intervals. The centers of circles that correspond to the third hierarchy levels are located at even intervals on a circle with the same center point as the second level circle, which the third levels belong to. The nodes of the subsequent levels are located in the same way. The proposed presentation method is successfully applied to a large-scale telecommunication network. Moreover, the results of an operating experiment with the proposed method show its effectiveness for presenting hierarchies of large-scale telecommunication networks.

A GaAs SPDT switch IC operating at a low power supply voltage of 2.7 V has been developed for use in 1.9 GHz band personal handy phone system (PHS). In combination with MESFETs with low on-resistance and high breakdown voltage, the switch IC adopts parallel-LC resonant circuits and utilizes both stacked FETs and an additional shunt capacitor at the receiver side in order to realize low insertion loss, high isolation and low distortion characteristics. An insertion loss of 0.55 dB and an isolation of 35.8 dB were obtained at 1.9 GHz. The IC also achieved an output power of 25.0 dBm at 1 dB gain compression point, a second order distortion of -54.3 dBc and an adjacent channel leakage power of -66 dBc at 600 kHz apart from 1.9 GHz at 19 dBm output power.

This paper describes the relation between the structure and the capability on mesh-connected computers with orthogonal broadcasting. It is shown that algorithms of maximum finding for the two-way communication model can be performed on the one-way communication model without increasing the time complexity.

This paper discribes the ISDN PROtocol Testing system (I-PROT). The system consists of translation & distribution function block, layer-2 fault surveillance function block, layer-3 fault surveillance function block, cause detection function block, and HMI. The system receives data from protocol monitors and detects the error recovery sequences, (we call "quasi-normal sequences"), as well as the sequences that do not follow the protocol specifications, (we call "abnormal sequences"). In the layer-3 fault surveillance function block, we use the protocol specification database whose records are converted from the state transition rules and added the judgment which classify the rules into the "normal" and "quasi-normal." We also show the classification method which is applicable to all connection-oriented protocol specifications. In the layer-2 fault surveillance function block, we explain the another easy detecting method. In the cause function block, we describe the partial pattern matching method to relate the protocol fault to the real cause of the fault. We built the prototype of the I-PROT and examine the turn around time (TAT) performance. As a result of the examination, we find the TAT of the I-PROT is directly proportional to the number of the frames analyzed by the system, and the system can reduce the load of the conventional manual analysis by the maintenance personnel.

Users of computer communication systems and their requirements are rapidly increasing and changing. It is desirable to have a development method which helps to make small changes in a design of a system to obtain another system which satisfies new requirement changes. We propose a flexible synthesis method which adopts designers' requirement changes in formal protocol specifications designed in LOTOS.

We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.

Several multiuser detectors have been recently proposed to combat multiple-access interference and near-far problem for CDMA systems. The performance of a multi-user receiver in combining the decorrelating decision-feedback scheme for a synchronous DS/CDMA system is considered. Using the Gaussian approximation on the multiple-access interference and amplitude estimation errors, we derive a closed form expression for the BER performance of the decorrelating decision-feedback detector in single-path Rayleigh fading channel and power controlled system. And, we show that our analysis agrees with the results of simulations. A modified decision-feedback detector is also proposed and analyzes. Numerical results show that the modified dicision-feedback detector proposed in this paper results in enhanced performance.

This paper proposes a prediction method for non-stationary time series data with time varying parameters. A modular structured type neural network is newly introduced for the purpose of grasping the changing property of time varying parameters. This modular structured neural network is constructed by the hierarchical combination of each neural network (NNT: Neural Network for Prediction of Time Series Data) and a neural network (NNW: Neural Network for Prediction of Weights). Next, we propose a reasonable method for determination of the length of the local stationary section by using the additive learning ability of neural networks. Finally, the validity and effectiveness of the proposed method are confirmed through simulation and actual experiments.

A buried gate AlGaAs/InGaAs heterojunction FET (HJFET) with gate breakdown voltage of 30 V was examined for high drain bias (higher than 10 V) operation. High breakdown voltage was realized due to the optimization of the narrow recess depth. A 1.4 mm HJFET has exhibited an output power of 30.2 dBm (1050 mW) with 50% power added efficiency (PAE) and 12.1 dB linear gain at 12 GHz with a 13 V drain bias. An internal matching circuit for a 16.8 mm HJFET was designed using a large-signal load impedance determined from load-pull measurement. The 16.8 mm internally-matched HJFET has delivered 38.9 dBm (7.8 W) output power with 46% PAE and 11.6 dB linear gain at 12 GHz with a drain bias of 13 V. This is the first report of higher than 10 V operation of an X- and Ku-band power HJFET with the excellent power performance.

Conformance testing is to see if the protocol implementation conforms to its specification. A lot of test sequences have been developed for testing centers. Yet directly applying these test sequences to the simple testing system in laboratories suffers from the frequently-occurred synchronization problems. This paper proposes a new technique to disconnect a test sequence into segments based on their functions, and reconnects them into a new test sequence that simulates these functions yet suffers less from the synchronization problems.