The Resource Auction Multiple Access (RAMA) protocol was proposed by N. Amitay for fast resource allocations to mobile terminals. We have proposed an Enhanced RAMA (ERAMA) protocol yielding lower system delay and delay variations than does the RAMA protocol. In this paper, we model a two-stage queueing network to evaluate the performance of the proposed protocol in terms of mean access delay, mean buffering delay, talk spurt loss ratio, and channel utilization, under homogeneous voice connections. The analytical results yield upper estimates for the various performance indices, compared with those of the simulations.

A current-mode analog chaos circuit realizing a Henon map is proposed. The synthesis of the proposed analog chaos circuit is based on switched-current (SI) BiCMOS techniques. For the proposed circuit, simulations are performed concerning the return map and the bifurcation diagram. In these simulations, the existence of chaos is confirmed using the Liapunov exponent. The proposed circuit is built with commercially-available IC's. The return maps and bifurcation diagram are measured in experiments. The proposed circuit is integrable by a standard BiCMOS technology.

Device design to reduce the abnormal operation due to the floating body effect was investigated for 0.2µm fully depleted SOI-MOSFETs, by use of a two-dimensional device simulator. It was found that the critical drain voltage and the critical multiplication factor for the floating body effect strongly depend on the potential profile which is related to the doping concentration. Based on simulation results, a nonuniformly doped structure is proposed for optimizing the potential profile to reduce the floating body effect. The applicable voltage of this structure was found to be 40% higher than that of the uniformly doped structure. A simple model is also derived to explain the above result.

SOI (Silicon On Insulator) transistors have certain problems due to the floating body. These problems become remarkable in the memory cell transistors of DRAMs. We propose a new refresh function and circuits for SOI DRAMs. And we obtained the result that this refresh function removed the injected hole from the body region and gave stable body potential by the device simulation. Therefore we can realize the long data retention characteristics for SOI DRAMs without an increase of the memory cell area or an additional refresh operation.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

We propose a new bit timing recovery (BTR) scheme, what we call Step Sampled BTR (SSBTR), that can lower the sampling clock frequency and shorten the clock phase convergence time, for burst signals in high bit rate wireless access systems. The SSBTR scheme has the following characteristics. A sine wave resulting from the BTR code passing through a Nyquist Transmission System is always used, the sampling clock has a lower frequency than the system clock, and the clock phase of Intermediate Frequency (IF) signal input can be estimated from as few as 3 sampled data. The SSBTR scheme corrects the clock phase only once in a burst signal. Therefore, in some wireless access systems, some kind of operation must be performed after the SSBTR, in order to deal with long burst signals, instability of the system clock, and so on. In other wireless access systems that do not have these problems, clock phase can be fixed by the SSBTR scheme alone. The preformance of the SSBTR scheme with respect to additive white Gaussian noise (AWGN) was examined by computer simulation. In addition, when SSBTR is implemented in hardware, there are imperfections in the circuitry that lead to phase estimation error and thus deterioration, so we studied the effects of several such imperfections by computer simulation. The results of these simulations clarify the performance of the SSBTR scheme.

This paper presents an adaptive coding rate trellis-coded octal phase-shift keying system with rates of 1/3, 1/2, 2/3, and 5/6, under the restriction of a constant transmission bit rate, where the ratio between the informaion bits and error-correcting redundant bits varies according to channel conditions. This system has the advantage of using a simple modem configuration. Because it has no need to change modulation type, transmitter/receiver filters, and clock and carrier recovery circuits, and it can use a convenient Read-Only-Memory table encoder. As for code design, the trellis structures and its signal assignments for rates of 1/3, 1/2, and 5/6 are proposed and investigated, and their BER performances are estimated. As a result, when the system requirement is to keep the bit error rate of 10-4, this system can operate at the lower Eb/No value of 1.5dB on the reduction of transmitting information bits.

This paper provides an architectural study of optical multiple-ring trunk-transmission networks using high-speed Time Division Multiplexing (TDM), and proposes two algorithms for distributed control environments. We propose a path-setup algorithm that uses Token protocol over Section Overhead (SOH) bytes, by which network-nodes communicate with each other to reserve bandwidth. A classified path restoration algorithm is also proposed that offers 3 path classes in terms of restoration performance. Class A paths, the most reliable, never lose any bit even against unpredictable disasters. They are realized by path-duplication at the source node, route diversity,and hitless switching at the destination node. Class B paths are restored by re-routing, where the original path-setup algorithm is reused. Class C paths are the most economical because a failed path is restored by maintenance action.

We have constructed a new concept device with combination of ferroelectric and ferromagnetic materials by a laser ablation technique. An ideal hetero-epitaxy can be obtained owing to the similar crystal structure of perovskite type ferroelectric Pb (Zr, Ti) O3; (so called PZT) and ferromagnetic (La, Sr) MnO3. The ferromagnetic (La, Sr) MnO3 compounds are well known for their colossal magnetoresistance (CMR) properties. The CMR effect is strongly affected by the lattice stress. The PZT, on the other hand, is famous for its large piezoelectrics. We can introduce the lattice stress easily by applying voltage for the piezoelectric compounds. In the heterostructured ferromagnetic/ferroelectric devices, there are remarkable interesting phenomena. Electric properties of the ferromagnetic material can be controlled by piezoelectric effect via distortion of crystal structure.

We propose a memory-based processor called a Functional Memory Type Parallel Processor for vector quantization (FMPP-VQ). The FMPP-VQ is intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search on vector quantization. In the nearest neighbor search, we look for a vector nearest to an input one among a large number of code vectors. The FMPP-VQ has as many PEs (processing elements, also called "blocks") as code vectors. Thus distances between an input vector and code vectors are computed simultaneously in every PE. The minimum value of all the distances is searched in parallel, as in conventional CAMs. The computation time does not depend on the number of code vectors. In this paper, we explain the detail of the architecture of the FMPP-VQ, its performance and its layout density. We designed and fabricated an LSI including four PEs. The test results and performance estimation of the LSI are also reported.

A modified fully-digital code tracking loop is proposed in this paper for direct-sequence spread-spectrum signaling on a frequency-selective fading channel. A data-modulated channel estimator is used to cope with the time-varying Rayleigh fading effect and the data modulation effect, and extract the desired error signal from each path independently in the multipath environments. By taking advantage of the inherent diversity with the maximal ratio combining (MRC) or a proposed Even/odd maximal ratio combining (EMRC) technique, this modified code tracking loop can avoid the problem due to the drift or flutter effects of the error characteristics, and provide better performance on frequency selective fading channels. Extensive computer simulation has verified the analysis and indicated very attractive behavior of the proposed digital tracking loop.

A suggestion for creating an excitable/oscillatory field with solid-state material is proposed. In essence, the idea is to make a spatial array of "mesoscopic particles" with the characteristics of a first-order phase transition. A theoretical computation shows that an auto-wave, or excitable wave, is generated in such an excitable field. A simple example of using this system as a diode in information flow is given.

A digital neuro chip with proliferating neuron architecture is described. This chip simulates a neural network model called the adaptive segmentation of quantizer neuron architecture (ASQA). It has proliferating neurons, and can automatically form the optimum network structure for recognition according to the input data. To develop inexpensive commercial hardware and implement a proliferating neuron architecture, we adopt a virtual neuron system for hardware implementation. Namely, this chip is implemented with only an arithmetic unit for network computations, and the network information such as network structure, synaptic weights and so on, are stored in external memories. We devise our original architecture which can efficiently memorize the network information, and moreover, construct a structured network using the ASQA model. As a result, we can recognize about 3,000 Kanji characters using a single chip and a recognition speed of 4.6 msec/character is achieved on a PC.

In this paper, we propose a quasi-optimum multiuser detector using co-channel interference cancellation technique in an asynchronous code-division multiple-access communication system, and evaluate its performance by computer simulations. In the proposed detector, maximum likelihood sequence estimation is performed to compare the original received signal with replicas of the signal which are produced from the demodulation data bit sequence of a co-channel interference canceller. In several conditions, the proposed detector is compared with the co-channel interference canceller, and it is shown that the average bit error rate characteristics of the propose detector are improved considerably.

We propose a soft decision Viterbi decoding scheme and a self-interference cancellation method applicable to a Parallel Combinatory CDMA (PC-CDMA) system. In this decoding scheme, branch metric is calculated for every bit by weighting the output levels of the PC-CDMA correlators so as to enable an effective soft decision capability to the system. The effectivity of this scheme is then further enhanced by the use of a simple pseudo-random bit interleaving scheme. Moreover, to increase the capacity of the PC-CDMA system, we propose a simple self-interference cancellation method for self-induced cross-correlation arising from the multipath environment. This further enhances the efficacy of the decoding scheme because the false contributions of the self-induced cross-correlation component are removed from the branch metric prior to soft decision Viterbi decoding. Finally, we simulated a possible PC-CDMA system with a user data rate of 1.92Mbps, transmitting it at a chip rate of 3.84Mcps and at 7.68Mcps under a multipath-Rayleigh fading interference environment. For a chip rate of 7.68Mcps, BER after Viterbi decoding is less than 3.2e-7 even without the use of interference cancellation. For a chip rate of 3.84Mcps, BER after Viterbi decoding with interference cancellation is 1.0e-4.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

We propose a new scanning method for image signals using a tree structure of automata. The tree is scanned selectively along the signal path for realizing both lower power consumption and a kind of image compression by skipping nonactive elements. We designed the node automata along with photo-detectors of 3232 in a 7.2 mm7.2 mm chip using a 1.5µm CMOS technology. We demonstrate applications of the tree structure using its feature of selective activation; a moving picture compression using inter-frame difference, an adaptive resolution scan like human eyesight and a motion compensation as examples.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

Applying ARQ to real time video communication can significantly increase transmission delay due its retransmission operations. We analyze this delay and propose an adaptive error control scheme that uses acknowledgment from the receiver to reduce the delay. We evaluate this scheme using a computer simulation and show that the proposed scheme can reduce the delay by controlling the amount of video data by changing the quantization step size and video frame skipping. It also offers acceptable video quality as confirmed by a subjective evaluation test.

This paper proposes the use, in integrated wireless systems, of the Reserved Idle Signal Multiple Access with Collision Resolution (R-ISMA/CR) protocol for applications in future multimedia mobile communications. It is applied to the integrated voice and data wireless system. Moreover, the consideration is made of the integrated voice and the low-bit video wireless system in R-ISMA/CR. To integrate video we employed not only a packed discard for video packets when the video packet delay is more than a threshold value, but also the connection packet (CP) technique for improving the channel utilization. Finally the integration of voice, data, and low-bit-video wireless system in R-ISMA/CR is considered. The performance are evaluated mainly by simulations.