Device-to-device (D2D) relay enhances the capacity of a mobile network. If the channel quality of a user equipment (UE) is bad, the UE asks a neighbor to get its data from the base station and forward the data to it by using D2D communication. Since cellular and D2D communication can share spectrum resources, the spectral efficiency will rise. As UEs are owned by self-interested users, they may not provide relay services gratis. Thus, some incentive methods let UEs exchange tokens to buy and sell relay services. However, they assume that each relay service is worth one token and offers a fixed data rate, which lacks flexibility. Through the law of supply and demand, this paper proposes an economy aware token-based incentive (EAT-BI) strategy. A supplier (i.e., the service provider) charges different prices for its relay service with different rates. A consumer (i.e., the service requestor) takes different policies to choose a supplier based on its tokens and may bargain with suppliers to avoid starvation. Simulation results show that EAT-BI can efficiently promote D2D relay use and increase throughput under different mobility models of UEs.

Multi-core fiber (MCF) is one of the most promising candidates for achieving ultra-wideband optical transmission in the near future. To build a network using MCF, a high-performance and reliable MCF connector is indispensable. We have developed an SC-type optical connector for MCF and confirmed its excellent optical performance, mechanical durability, and environmental reliability. To put the communication system using MCF into practical use, it is necessary to establish a procedure for measuring the initial connection characteristics. Fan-in / fan-out (FIFO) devices are indispensable for measuring the connection characteristics of MCF connectors. To measure the return loss of the MCF connector, it is necessary to remove the influence of reflection at the FIFO itself and at the connection points with the FIFO. In this paper, we compare four types of return loss measurement procedures (three usual method and a new method we proposed) and find that most stable measurement method involves using our new method, the OCWR method without FIFO. The OCWR method without FIFO is considered to be the most advantageous when used for outgoing inspection of connectors. The reason is that it eliminates the measurement uncertainty caused by the FIFO and enables speedy measurement.

In this study, we propose an accurate range-Doppler analysis algorithm for moving multiple objects in a short range using microwave (including millimeter wave) radars. As a promising Doppler analysis for the above model, we previously proposed a weighted kernel density (WKD) estimator algorithm, which overcomes several disadvantages in coherent integration based methods, such as a trade-off between temporal and frequency resolutions. However, in handling multiple objects like human body, it is difficult to maintain the accuracy of the Doppler velocity estimation, because there are multiple responses from multiple parts of object, like human body, incurring inaccuracies in range or Doppler velocity estimation. To address this issue, we propose an iterative algorithm by exploiting an output of the WKD algorithm. Three-dimensional numerical analysis, assuming a human body model in motion, and experimental tests demonstrate that the proposed algorithm provides more accurate, high-resolution range-Doppler velocity profiles than the original WKD algorithm, without increasing computational complexity. Particularly, the simulation results show that the cumulative probabilities of range errors within 10mm, and Doppler velocity error within 0.1m/s are enhanced from 34% (by the former method) to 63% (by the proposed method).

SiC-MOSFETs are being increasingly implemented in power electronics systems as low-loss, fast switching devices. Despite the advantages of an SiC-MOSFET, its large dv/dt or di/dt has fear of electromagnetic interference (EMI) noise. This paper proposes and demonstrates a simple and robust gate driver that can suppress ringing oscillation and surge voltage induced by the turn-off of the SiC-MOSFET body diode. The proposed gate driver utilizes the channel leakage current methodology (CLC) to enhance the damping effect by elevating the gate-source voltage (VGS) and inducing the channel leakage current in the device. The gate driver can self-adjust the timing of initiating CLC operation, which avoids an increase in switching loss. Additionally, the output voltage of the VGS elevation circuit does not need to be actively controlled in accordance with the operating conditions. Thus, the circuit topology is simple, and ringing oscillation can be easily attenuated with fixed circuit parameters regardless of operating conditions, minimizing the increase in switching loss. The effectiveness and versatility of proposed gate driver were experimentally validated for a wide range of operating conditions by double and single pulse switching tests.

For formulating Quadratic Knapsack Problems (QKPs) into the form of Quadratic Unconstrained Binary Optimization (QUBO), it is necessary to introduce an integer variable, which converts and incorporates the knapsack capacity constraint into the overall energy function. In QUBO, this integer variable is encoded with auxiliary binary variables, and the encoding method used for it affects the behavior of Simulated Annealing (SA) significantly. For improving the efficiency of SA for QKP instances, this paper first visualized and analyzed their annealing processes encoded by conventional binary and unary encoding methods. Based on this analysis, we proposed a novel hybrid encoding (HE), getting the best of both worlds. The proposed HE obtained feasible solutions in the evaluation, outperforming the others in small- and medium-scale models.

Multilayer perceptron (MLP) is a basic neural network model that is used in practical industrial applications, such as network intrusion detection (NID) systems. It is also used as a building block in newer models, such as gMLP. Currently, there is a demand for fast training in NID and other areas. However, in training with numerous GPUs, the problems of power consumption and long training times arise. Many of the latest deep neural network (DNN) models and MLPs are trained using a backpropagation algorithm which transmits an error gradient from the output layer to the input layer such that in the sequential computation, the next input cannot be processed until the weights of all layers are updated from the last layer. This is known as backward locking. In this study, a weight parameter update mechanism is proposed with time delays that can accommodate the weight update delay to allow simultaneous forward and backward computation. To this end, a one-dimensional systolic array structure was designed on a Xilinx U50 Alveo FPGA card in which each layer of the MLP is assigned to a processing element (PE). The time-delay backpropagation algorithm executes all layers in parallel, and transfers data between layers in a pipeline. Compared to the Intel Core i9 CPU and NVIDIA RTX 3090 GPU, it is 3 times faster than the CPU and 2.5 times faster than the GPU. The processing speed per power consumption is 11.5 times better than that of the CPU and 21.4 times better than that of the GPU. From these results, it is concluded that a training accelerator on an FPGA can achieve high speed and energy efficiency.

This study presents a selective data-compression interconnection network to boost its performance. Data compression virtually increases the effective network bandwidth. One drawback of data compression is a long latency to perform (de-)compression operation at a compute node. In terms of the communication latency, we explore the trade-off between the compression latency overhead and the reduced injection latency by shortening the packet length by compression algorithms. As a result, we present to selectively apply a compression technique to a packet. We perform a compression operation to long packets and it is also taken when network congestion is detected at a source compute node. Through a cycle-accurate network simulation, the selective compression method using the above compression algorithms improves by up to 39% the network throughput with a moderate increase in the communication latency of short packets.

In this paper, we propose a multi-domain learning model for action recognition. The proposed method inserts domain-specific adapters between layers of domain-independent layers of a backbone network. Unlike a multi-head network that switches classification heads only, our model switches not only the heads, but also the adapters for facilitating to learn feature representations universal to multiple domains. Unlike prior works, the proposed method is model-agnostic and doesn't assume model structures unlike prior works. Experimental results on three popular action recognition datasets (HMDB51, UCF101, and Kinetics-400) demonstrate that the proposed method is more effective than a multi-head architecture and more efficient than separately training models for each domain.

Graph layout is a critical component in graph visualization. This paper proposes GRAPHULY, a graph u-nets-based neural network, for end-to-end graph layout generation. GRAPHULY learns the multi-level graph layout process and can generate graph layouts without iterative calculation. We also propose to use Laplacian positional encoding and a multi-level loss fusion strategy to improve the layout learning. We evaluate the model with a random dataset and a graph drawing dataset and showcase the effectiveness and efficiency of GRAPHULY in graph visualization.

Channel state information (CSI) acquisition at the transmitter side is a major challenge in massive MIMO systems for enabling high-efficiency transmissions. To address this issue, various CSI feedback schemes have been proposed, including limited feedback schemes with codebook-based vector quantization and explicit channel matrix feedback. Owing to the limitations of feedback channel capacity, a common issue in these schemes is the efficient representation of the CSI with a limited number of bits at the receiver side, and its accurate reconstruction based on the feedback bits from the receiver at the transmitter side. Recently, inspired by successful applications in many fields, deep learning (DL) technologies for CSI acquisition have received considerable research interest from both academia and industry. Considering the practical feedback mechanism of 5th generation (5G) New radio (NR) networks, we propose two implementation schemes for artificial intelligence for CSI (AI4CSI), the DL-based receiver and end-to-end design, respectively. The proposed AI4CSI schemes were evaluated in 5G NR networks in terms of spectrum efficiency (SE), feedback overhead, and computational complexity, and compared with legacy schemes. To demonstrate whether these schemes can be used in real-life scenarios, both the modeled-based channel data and practically measured channels were used in our investigations. When DL-based CSI acquisition is applied to the receiver only, which has little air interface impact, it provides approximately 25% SE gain at a moderate feedback overhead level. It is feasible to deploy it in current 5G networks during 5G evolutions. For the end-to-end DL-based CSI enhancements, the evaluations also demonstrated their additional performance gain on SE, which is 6%-26% compared with DL-based receivers and 33%-58% compared with legacy CSI schemes. Considering its large impact on air-interface design, it will be a candidate technology for 6th generation (6G) networks, in which an air interface designed by artificial intelligence can be used.

Industrial networks need to provide reliable communication services, usually in a redundant transmission (RT) manner. In the past few years, several device-redundancy-based, layer 2 solutions have been proposed. However, with the evolution of industrial networks to the Industrial Internet, these methods can no longer work properly in the non-redundancy, layer 3 environments. In this paper, an SDN-based reliable communication framework is proposed for the Industrial Internet. It can provide reliable communication guarantees for mission-critical applications while servicing non-critical applications in a best-effort transmission manner. Specifically, it first implements an RT-based reliable communication method using the Industrial Internet's link-redundancy feature. Next, it presents a redundant synchronization mechanism to prevent end systems from receiving duplicate data. Finally, to maximize the number of critical flows in it (an NP-hard problem), two ILP-based routing & scheduling algorithms are also put forward. These two algorithms are optimal (Scheduling with Unconstrained Routing, SUR) and suboptimal (Scheduling with Minimum length Routing, SMR). Numerous simulations are conducted to evaluate its effectiveness. The results show that it can provide reliable, duplicate-free services to end systems. Its reliable communication method performs better than the conventional best-effort transmission method in terms of packet delivery success ratio in layer 3 networks. In addition, its scheduling algorithm, SMR, performs well on the experimental topologies (with average quality of 93% when compared to SUR), and the time overhead is acceptable.

Named Data Networking (NDN) uses name to indicate content mechanism to divide content, and uses content names for routing and addressing. However, the traditional network devices that support the TCP/IP protocol stack and location-centric communication mechanisms cannot support functions such as in-network storage and multicast distribution of NDN effectively. The performance of NDN routers designed for specific functional platforms is limited, and it is difficult to deploy on a large scale, so the NDN network can only be implemented by software. With the development of data plane languages such as Programmable Protocol-Independent Packet Processors (P4), the practical deployment of NDN becomes achievable. To ensure efficient data distribution in the network, this paper proposes a protocol-independent multicast method according to each binary bit. The P4 language is used to define a bit vector in the data packet intrinsic metadata field, which is used to mark the requested port. When the requested content is returned, the routing node will check which port has requested the content according to the bit vector recorded in the register, and multicast the Data packet. The experimental results show that bitwise multicast technology can eliminate the number of flow tables distributed compared with the dynamic multicast group technology, and reduce the content response delay by 57% compared to unicast transmission technology.

Edge computing, which has been gaining attention in recent years, has many advantages, such as reducing the load on the cloud, not being affected by the communication environment, and providing excellent security. Therefore, many researchers have attempted to implement neural networks, which are representative of machine learning in edge computing. Neural networks can be divided into inference and learning parts; however, there has been little research on implementing the learning component in edge computing in contrast to the inference part. This is because learning requires more memory and computation than inference, easily exceeding the limit of resources available for edge computing. To overcome this problem, this research focuses on the optimizer, which is the heart of learning. In this paper, we introduce our new optimizer, hardware-oriented logarithmic momentum estimation (Holmes), which incorporates new perspectives not found in existing optimizers in terms of characteristics and strengths of hardware. The performance of Holmes was evaluated by comparing it with other optimizers with respect to learning progress and convergence speed. Important aspects of hardware implementation, such as memory and operation requirements are also discussed. The results show that Holmes is a good match for edge computing with relatively low resource requirements and fast learning convergence. Holmes will help create an era in which advanced machine learning can be realized on edge computing.

Recently, robust speech recognition for real-world applications has attracted much attention. This paper proposes a robust speech recognition method based on the teacher-student learning framework for domain adaptation. In particular, the student network will be trained based on a novel optimization criterion defined by the encoder outputs of both teacher and student networks rather than the final output posterior probabilities, which aims to make the noisy audio map to the same embedding space as clean audio, so that the student network is adaptive in the noise domain. Comparative experiments demonstrate that the proposed method obtained good robustness against noise.

This paper presents a novel frequency-controlled beam steering scheme for a phased-array antenna system (PAS). The proposed scheme employs phase-controlled carrier signals to form the PAS beam. Two local oscillators (LOs) and delay lines are used to generate the carrier signals. The carrier of one LO is divided into branches, and then the divided carriers passing through the corresponding delay lines have the desired phase relationship, which depends on the oscillation frequency of the LO. To confirm the feasibility of the scheme, four-branch PAS transmitters are configured and tested in a 10-GHz frequency band. The results verify that the formed beam is successfully steered in a wide range, i.e., the 3-dB beamwidth of approximately 100 degrees, using LO frequency control.

To the best of our knowledge, there have been very few work on computational algorithms for the core or its variants in MC-nets games. One exception is the work by [Hirayama, et.al., 2014], where a constraint generation algorithm has been proposed to compute a payoff vector belonging to the least core. In this paper, we generalize this algorithm into the one for finding a payoff vector belonging to ϵ-core with pre-specified bound guarantee. The underlying idea behind this algorithm is basically the same as the previous one, but one key contribution is to give a clearer view on the pricing problem leading to the development of our new general algorithm. We showed that this new algorithm was correct and never be trapped in an infinite loop. Furthermore, we empirically demonstrated that this algorithm really presented a trade-off between solution quality and computational costs on some benchmark instances.

With the development of blockchain technology, the automatic generation of smart contract has become a hot research topic. The existing smart contract automatic generation technology still has improvement spaces in complex process, third-party specialized tools required, specific the compatibility of code and running environment. In this paper, we propose an automatic smart contract generation method, which is domain-oriented and configuration-based. It is designed and implemented with the application scenarios of government service. The process of configuration, public state database definition, code generation and formal verification are included. In the Hyperledger Fabric environment, the applicability of the generated smart contract code is verified. Furthermore, its quality and security are formally verified with the help of third-party testing tools. The experimental results show that the quality and security of the generated smart contract code meet the expect standards. The automatic smart contract generation will “elegantly” be applied on the work of anti-disclosure, privacy protection, and prophecy processing in government service. To effectively enable develop “programmable government”.

The Nyquist folding receiver (NYFR) is a novel analog-to-information architecture, which can achieve wideband receiving with a small amount of system resource. The NYFR uses a radio frequency (RF) non-uniform sampling to realize wideband receiving, and the practical RF non-uniform sample pulse train usually contains an aperture. Therefore, it is necessary to investigate the aperture impact on the NYFR output. In this letter, based on the NYFR output signal to noise ratio (SNR), the aperture impact on the NYFR is analyzed. Focusing on the aperture impact, the corresponding NYFR output signal power and noise power are given firstly. Then, the relation between the aperture and the output SNR is analyzed. In addition, the output SNR distribution containing the aperture is investigated. Finally, combing with a parameter estimation method, several simulations are conducted to prove the theoretical aperture impact.

Deep Neural Network (DNN) is widely used for computer vision tasks, such as image classification, object detection, and segmentation. DNN accelerator on FPGA and especially Convolutional Neural Network (CNN) is a hot topic. More research and education should be conducted to boost this field. A starting point is required to make it easy for new entrants to join this field. We believe that FPGA-based Autonomous Driving (AD) motor cars are suitable for this because DNN accelerators can be used for image processing with low latency. In this paper, we propose an FPGA-based simple and open-source mini motor car system named RVCar with a RISC-V soft processor and a CNN accelerator. RVCar is suitable for the new entrants who want to learn the implementation of a CNN accelerator and the surrounding system. The motor car consists of Xilinx Nexys A7 board and simple parts. All modules except the CNN accelerator are implemented in Verilog HDL and SystemVerilog. The CNN accelerator is converted from a PyTorch model by our tool. The accelerator is written in C++, synthesizable by Vitis HLS, and an easy-to-customize baseline for the new entrants. FreeRTOS is used to implement AD algorithms and executed on the RISC-V soft processor. It helps the users to develop the AD algorithms efficiently. We conduct a case study of the simple AD task we define. Although the task is simple, it is difficult to achieve without image recognition. We confirm that RVCar can recognize objects and make correct decisions based on the results.

This brief presents A 16/32Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067mm2, while the proposed linearity enhanced part is 0.05×0.02mm2 and the total power consumption is 64.6mW with a 1.1V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.