In order to expect the single event occurrence on highly integrated CMOS memory circuit, quantitative evaluation of charge sharing between memory cells is needed. In this study, charge sharing area induced by heavy ion incident is quantitatively calculated by using device-simulation-based method. The validity of this method is experimentally confirmed using the charged heavy ion accelerator.

Locally repairable codes (LRCs) are a type of new erasure codes designed for modern distributed storage systems (DSSs). In order to obtain ternary LRCs of distance 6, firstly, we propose constructions with disjoint repair groups and construct several families of LRCs with 1 ≤ r ≤ 6, where codes with 3 ≤ r ≤ 6 are obtained through a search algorithm. Then, we propose a new method to extend the length of codes without changing the distance. By employing the methods such as expansion and deletion, we obtain more LRCs from a known LRC. The resulting LRCs are optimal or near optimal in terms of the Cadambe-Mazumdar (C-M) bound.

This paper presents the first attribute-based signature (ABS) scheme in which the correspondence between signers and signatures is captured in an arithmetic model of computation. Specifically, we design a fully secure, i.e., adaptively unforgeable and perfectly signer-private ABS scheme for signing policies realizable by arithmetic branching programs (ABP), which are a quite expressive model of arithmetic computations. On a more positive note, the proposed scheme places no bound on the size and input length of the supported signing policy ABP's, and at the same time, supports the use of an input attribute for an arbitrary number of times inside a signing policy ABP, i.e., the so called unbounded multi-use of attributes. The size of our public parameters is constant with respect to the sizes of the signing attribute vectors and signing policies available in the system. The construction is built in (asymmetric) bilinear groups of prime order, and its unforgeability is derived in the standard model under (asymmetric version of) the well-studied decisional linear (DLIN) assumption coupled with the existence of standard collision resistant hash functions. Due to the use of the arithmetic model as opposed to the boolean one, our ABS scheme not only excels significantly over the existing state-of-the-art constructions in terms of concrete efficiency, but also achieves improved applicability in various practical scenarios. Our principal technical contributions are (a) extending the techniques of Okamoto and Takashima [PKC 2011, PKC 2013], which were originally developed in the context of boolean span programs, to the arithmetic setting; and (b) innovating new ideas to allow unbounded multi-use of attributes inside ABP's, which themselves are of unbounded size and input length.

The recent development of semiconductor technology has led to downsized, large-scaled and low-power VLSI systems. However, the incidence of soft errors has increased. Soft errors are temporary events caused by striking of α-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a new design of a DNU tolerant latch to resolve this issue by adding some transistors to the HLDTL latch.

Saliency detection is widely used in many vision tasks like image retrieval, compression and person re-identification. The deep-learning methods have got great results but most of them focused more on the performance ignored the efficiency of models, which were hard to transplant into other applications. So how to design a efficient model has became the main problem. In this letter, we propose parallel feature network, a saliency model which is built on convolution neural network (CNN) by a parallel method. Parallel dilation blocks are first used to extract features from different layers of CNN, then a parallel upsampling structure is adopted to upsample feature maps. Finally saliency maps are obtained by fusing summations and concatenations of feature maps. Our final model built on VGG-16 is much smaller and faster than existing saliency models and also achieves state-of-the-art performance.

In OFDM systems, link performance depends heavily on the estimation of symbol-timing and frequency offsets. Performance sensitivity to these estimates is a major drawback of OFDM systems. Timing errors destroy the orthogonality of OFDM signals and lead to inter-symbol interference (ISI) and inter-carrier interference (ICI). The interference due to timing errors can be exploited as a metric for symbol-timing synchronization. In this paper, we propose a novel method to extract interference components using a DFT of the upsampled OFDM signals. Mathematical analysis and formulation are given for the dependence of interference on timing errors. From a numerical analysis, the proposed interference estimation shows robustness against channel dispersion.

Image interpolation is one of the image upsampling technologies from a single input image. This technology obtains high resolution images by fitting functions or models. Although image interpolation methods are faster than other upsampling technologies, they tend to cause jaggies and blurs in edge and texture regions. Multi-surface Fitting is one of the image upsampling techniques from multiple input images. This algorithm utilizes multiple local functions and the weighted means of the estimations in each local function. Multi-surface Fitting obtains high quality upsampled images. However, its quality depends on the number of input images. Therefore, this method is used in only limited situations. In this paper, we propose an image interpolation method with both high quality and a low computational cost which can be used in many situations. We adapt the idea of Multi-surface Fitting for the image upsampling problems from a single input image. We also utilize local functions to reduce blurs. To improve the reliability of each local function, we introduce new weights in the estimation of the local functions. Besides, we improve the weights for weighted means to estimate a target pixel. Moreover, we utilize convolutions with small filters instead of the calculation of each local function in order to reduce the computational cost. Experimental results show our method obtains high quality output images without jaggies and blurs in short computational time.

With the scaling of technology, nanoscale CMOS integrated circuits are becoming more sensitive to single event double node upsets induced by charge sharing. A novel highly robust hardened latch design is presented that is fully resilient to single event double node upsets and single node upsets. The proposed latch employs multiple redundant C-elements to form a dual interlocked structure in which the redundant C-elements can bring the affected nodes back to the correct states regardless of the energy of the striking particle. Detailed HSPICE results confirm that the proposed latch features complete resilience to double node upsets and achieves an improved trade-off in terms of robustness, area, delay and power in comparison with previous latches. Extensive Monte Carlo simulations validate the proposed latch features as less sensitive to process, supply voltage and temperature variations.

As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.

This paper aims to support the cultivation of proper cognitive skills for academic English listening. First of all, this paper identified several listening strategies proved to be effective for cultivating listening skills through past research and builds up the respective strategy models, based on which we designed and developed various functional units as strategy objects, and the mashup environment where these function units can be assembled to serve as a personal learning environment. We also attached listening strategies and tactics to each object, in order to make learners aware of the related strategies and tactics applied during learning. Both short-term and mid-term case studies were carried out, and the data collected showed several positive results and some interesting indications.

In this paper, a self-recoverable, frequency-aware and cost-effective robust latch (referred to as RFC) is proposed in 45nm CMOS technology. By means of triple mutually feedback Muller C-elements, the internal nodes and output node of the latch are self-recoverable from single event upset (SEU), i.e. particle striking induced logic upset, regardless of the energy of the striking particle. The proposed robust latch offers a much wider spectrum of working clock frequency on account of a smaller delay and insensitivity to high impedance state. The proposed robust latch performs with lower costs regarding power and area than most of the compared latches. SPICE simulation results demonstrate that the area-power-delay product is 73.74% saving on average compared with previous radiation hardened latches.

We measure neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs) on Flip-Flops (FFs) in a 65-nm bulk CMOS process in order to evaluate dependence of MCUs on cell distance and well-contact density using four different shift registers. Measurement results by accelerated tests show that MCU/SEU is up to 23.4% and it is exponentially decreased by the distance between latches on FFs. MCU rates can be drastically reduced by inserting well-contact arrays between FFs. The number of MCUs is reduced from 110 to 1 by inserting well-contact arrays under power and ground rails.

As semiconductor devices scale into deep sub-micron regime, the reliability issue due to radiation-induced soft errors increases in on-chip memory systems. Neutron-induced soft errors transiently upset adjacent information of multiple cells in these systems. Although single error correction and double error detection (SEC--DED) codes have been employed to protect on-chip memories from soft errors, they are not sufficient against multiple cell upsets (MCUs). SEC--DED and double adjacent error correction (SEC--DED--DAEC) codes have recently been proposed to address this problem. However, these codes do not the resolve mis-correction of double non-adjacent errors because syndromes for double non-adjacent errors are equal to that of double adjacent errors. The occurrence of this mis-correction in region of critical memory section such as operating systems may lead to system malfunction. To eliminate mis-correction, the syndrome spaces for double adjacent and double non-adjacent errors are not shared using the matrix with reversed colexicographic order. The proposed codes are implemented using hardware description language and synthesized using 32 nm technology library. The results show that there is no mis-correction in the proposed codes. In addition, the performance enhancement of the decoder is approximately 51.9% compared to double error correction codes for on-chip memories. The proposed SEC--DED--DAEC codes is suitable for protecting on-chip memory applications from MCUs-type soft errors.

This paper describes a soft-error tolerant and margin-enhanced nMOS-pMOS reversed 6T SRAM cell. The 6T SRAM bitcell comprises pMOS access and driver transistors, and nMOS load transistors. Therefore, the nMOS and pMOS masks are reversed in comparison with those of a conventional bitcell. In scaled process technology, The pMOS transistors present advantages of small random dopant fluctuation, strain-enhanced saturation current, and small soft-error sensitivity. The four-pMOS and two-nMOS structure improves the soft-error rate plus operating margin. We conduct SPICE and neutron-induced soft-error simulations to evaluate the n-p reversed 6T SRAM bitcell in 130-nm to 22-nm processes. At the 22-nm node, a multiple-cell-upset and single-bit-upset SERs are improved by 34% and 51% over a conventional 6T cell. Additionally, the static noise margin and read cell current are 2.04× and 2.81× improved by leveraging the pMOS benefits.

We introduce the notion of 'Composition', 'Union' and 'Division' of cellular automata on groups. A kind of notions of compositions was investigated by Sato [10] and Manzini [6] for linear cellular automata, we extend the notion to general cellular automata on groups and investigated their properties. We observe the all unions and compositions generated by one-dimensional 2-neighborhood cellular automata over Z2 including non-linear cellular automata. Next we prove that the composition is right-distributive over union, but is not left-distributive. Finally, we conclude by showing reformulation of our definition of cellular automata on group which admit more than three states. We also show our formulation contains the representation using formal power series for linear cellular automata in Manzini [6].

The notion of pseudo-free groups was first introduced and formalized by Hohenberger and Rivest in order to unify cryptographic assumptions. Catalano, Fiore and Warinschi proposed a generalized notion called adaptive pseudo-free groups, and showed that the RSA group $Z_N^ imes$ is adaptive pseudo-free with some specific parametric distribution under the strong RSA assumption. In this paper, we develop an alternative parametric distribution and show that the RSA group $Z_N^ imes$ is adaptive pseudo-free with the parametric distribution under the RSA assumption rather than the strong RSA assumption.

This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-centered 6T SRAM cells.

In this paper we show that self synchronous circuits can provide robust operation in both soft error prone and low voltage operating environments. Self synchronous circuits are shown to be self checking, where a soft error will either cause a detectable error or halt operation of the circuit. A watchdog circuit is proposed to autonomously detect dual-rail '11' errors and prevent propagation, with measurements in 65 nm CMOS showing seamless operation from 1.6 V to 0.37 V. Compared to a system without the watchdog circuit size and energy-per-operation is increased 6.9% and 16% respectively, while error tolerance to noise is improved 83% and 40% at 1.2 V and 0.4 V respectively. A circuit that uses the dual-pipeline circuit style as redundancy against permanent faults is also presented and 40 nm CMOS measurement results shows correct operation with throughput of 1.2 GHz and 810 MHz at 1.1 V before and after disabling a faulty pipeline stage respectively.

This paper proposes a novel method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of application circuits onto coarse-grained reconfigurable architectures (CGRAs). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the node parameters which characterize impact of the SEU in the node on the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.

This paper proposes a dynamic bandwidth allocation algorithm that improves the network performance and bandwidth sharing efficiency in the upstream channels of a hybrid passive optical network (PON) that combines a fiber-to-the-home (FTTH) access network and wireless sensor networks (WSNs). The algorithm is called the adaptive limited dynamic bandwidth allocation (ALDBA) algorithm. Unlike existing algorithms, the ALDBA algorithm is not limited to controlling just FTTH access networks, it also supports WSNs. For the proposed algorithm, we investigate the difference in the lengths of generated data packets between the FTTH terminals and sensor nodes of WSN to effectively evaluate the end-to-end average packet delay, bandwidth utilization, time jitter, and upstream efficiency. Two variants of the proposed algorithm and a limited service (LS) scheme, which is an existing well-known algorithm, are compared under non-uniform traffic conditions without taking into consideration priority scheduling. We demonstrate the proposed scheme through simulation by generating a realistic network traffic model, called self-similar network traffic. We conducted a detailed simulation using several performance parameters to validate the effectiveness of the proposed scheme. The results of the simulation showed that both ALDBA variants outperformed the existing LS scheme in terms of average packet delay, bandwidth utilization, jitter, and upstream efficiency for both low and high traffic loads.