This paper describes the formation of ultra-thin tantalum oxide capacitors, using rapid thermal nitridation (RTN) of the storage-node polycrystalline-silicon surface prior to low-pressure chemical vapor deposition of tantalum oxide, using penta-ethoxy-tantalum [(Ta(OC2H5)5) and oxygen gas mixture. The films are annealed at 600-900 in dry O2 atmosphere. Densification of the as-deposited film by annealing in dry O2 is indispensable to the formation of highly reliable ultra-thin tantalum oxide capacitors. The RTN treatment reduces the SiO2 equivalent thickness and leakage current of the tantalum oxide film, and improves the time dependent dielectric breakdown characteristics of the film.

A local area network (LAN) can now provide high-speed data communications in a local area environment to establish distributed processing among personal computers and workstations, and the need for interconnecting LANs, which are geographically distributed, is naturally arising. Asynchronous Transfer Mode (ATM) technology has been widely recognized as a promising way to provide the high-speed wide area networks (WAN) for Broadband Integrated Services Digital Network (B-ISDN), and the commercial service offerings are expected in the near future. The ATM network seems to have a capability as a backbone network for interconnecting LANs, and the LAN interconnection is expected to be the first service in ATM networks. However, there remain some technical challenges for this purpose; one of the main difficulties in LAN interconnection is the support of connectionless traffic by the ATM network, which is basically a connection-oriented network. Another one is the way of achieving the very high-speed data transmission over the ATM network. In this paper, we first discuss a LAN internetworking methodology based on the current technology. Then, the recent deployments of LAN interconnection methods through B-ISDN are reviewed.

This paper proposes the Total High Performance Time as a performance-related reliability measure in degradable/recoverable real-time systems. This measure reflects the effect of system behavior in pending states that are temporary states between the normal state and degraded states where the system operates in a degraded mode as a consequence of component failures. Such systems have to perform not only normal procedures but also error/recovery procedures in pending states, so the performance there is lower than that in the degraded states. In real-time systems, if performance is less than a lower limit, the response time for on-line transactions cannot meet the deadline. The consequences of failing to meet the deadline could be system failure. Therefore, the system reliability is affected significantly by whether the performance there is higher than the lower limit or not. A state where the level of performance is higher than the lower limit is called a High Performance State. We define the Total High Performance Time as the total time that the system spends operating in High Performance States. Moreover, this paper explains how to utilize the Total High Performance Time in system design. We model a method of controlling a system in pending states by using Extended Stochastic Petri Nets and obtain the characteristics necessary for evaluating the Total High Performance Time by analyzing the model. This approach is applied to a storage system that controls mirrored disks, and shown to be helpful for designing a method of controlling a system in pending states, which has been considered difficult because of the trade-off between performance and reliability.

Connectionless service for LANs interconnection will be provided in ATM networks at an early stage of B-ISDN era. This service will be provided on connection oriented mode at ATM technology. To perform this service, ATM connections using the dedicated bandwidth for this service are established semi-permanently between the nodes accommodating LANs. On these ATM connections, connectionless service among LANs is provided. It is important for private networks to utilize this bandwidth efficiently for reducing communication cost. In this paper, the architecture to provide connectionless service in private networks is described. Next, the allocation schemes of the bandwidth for this service and their performance are considered. We discuss the following schemes and compare them. One scheme is to establish semi-permanent ATM connections between the nodes with LAN interfaces. The bandwidth for each connection is individually assigned between these nodes. In another scheme, CLSFs (Connection-Less Service Functions) are introduced for connectionless service and connections are established via CLSFs. We show the latter scheme is superior because it brings out the effectiveness of statistical multiplexing of ATM technology and it leads to the reduction of the allocated bandwidth.

This paper deals with methods for interconnection between two local private networks that are geographically separated. A scheme is first presented to chain low bit-rate physical circuits into one logical circuit, over which ATM cells are transmitted as if there is one circuit with a high bit-rate capacity. In particular, use of existing low bit-rate circuits, e.g., 384/1536 kbit/s PDH leased line services and N-ISDN switched channels, is considered. The paper discusses two methods to permit chaining of physical circuits, and identifies their advantages and applications. By using the ATM-based circuit-chaining method, dynamic capacity control of the interconnection is then introduced with the use of an ATM-based rate adaptation. This is intended to provide a flexible and cost-effective capacity control compared to the existing TDM-based control. It is also possible to realize non-stop operation of changing capacity by establishment and release of chained circuits, which will lead to high reliability and robustness of private networks. Finally, delay characteristics introduced by the method are evaluated based on a computer simulation which gives a short and acceptable delay.

IC performance simulation for statistical purpose is usually very time-consuming since the scale and complexity of IC have increased greatly in recent years. A common approach for reduction of simulation cost is aimed at the nature of simple modeling instead of actual circuit performance simulations. In this paper,a stochastic interpolation model (SIM) scheme is proposed which overcomes the drawbacks of the existing polynomial-based approximation schemes. First,the dependence of the R2press statistic upon a parameter in SIM is taken into account and by maximizing R2press this enables SIM to achieve the best approximation accuracy in the given sample points without any assumption on the sample data. Next, a sequential sampling strategy based on variance analysis is described to effectively construct SIM during its update process. In each update step, a new sample point with a maximal value of variance is added to the former set of the sample points. The update process will be continued until the desired approximation accuracy is reached. This would eventually lead to the realization of SIM with a quite small number of sample points. Finally, the coefficient of variance is introduced as another criterion for approximation accuracy check other than the R2press statistic. The effectiveness of presented implementation scheme is demonstrated by several numerical examples as well as a statistical circuit analysis example.

This paper describes a future private network service and the system configurations for providing it. Technologies and service trends in local area and wide area networks are shown. As network services become more diversified and integrated, it becomes more difficult for users to use the networks effectively. This paper shows how this problem can be solved by using virtual network technology to attain seamless networking. It also presents the concept of group networking among many parties, which can be used as the basis for a virtual private network.

The use of computers with private networks has accelerated the electronic storage of business information in office systems. With the rapid progress in processing capability and small sizing of the computer world, private networks are going to be more intelligent. The utilization of shared information is a key issue in modern organizations, in order to increase the productivity of white-collar workers. In the CSCW research field, it is said that informal and unstructured information is important in group work contexts but difficult to locate in a large organization. Many researchers are paying particular attention to the importance of support systems for such information. These kinds of information are called Organizational memory or Group Memory. Our research focuses on knowledge propagation with private networks in the organization. This means emphasis on the process; with which organized information or the ability to use information is circulated throughout the organization. Knowledge propagation has three issues: knowledge transmission, destination locating and source locating. To cope with these issues we developed FISH, which stands for Flexible Information Sharing and Handling system. FISH was designed to provide cooperative information sharing in a group work context and to explore knowledge propagation. FISH stores fragmental information as cards with multiple keywords and content. This paper discusses a three-layered model that describes computer supported knowledge transmission. Based on this model, three issues are discussed regarding knowledge propagation. FISH and its two-year experiment are described and knowledge propagation is explored based on the results of this experiment.

There has been growing interest in Broadband ISDN (B-ISDN) based on ATM (Asynchronous Transfer Mode) technologies, since ATM is expected to support a wide range of applications through high-speed and flexible multimedia communication capabilities. This paper reviews and discusses technical issues on multimedia communication protocols and services from the integration points of view of computer and communication technologies. An ISDN-based distributed multimedia and multi-party desktop conference system called MERMAID is introduced as an example which offers highly-sophisticated functions for remote collaborations among multiple users. This system, which was developed in early 1989 and has been used for daily research work since then, involves B-ISDN key technologies related to multimedia and multicast protocols, and computer architecture for groupware applications.

In this paper, we study a dynamic bandwidth control which is expected an effective use of network resources in transmitting highly bursty traffic generated by, e.g., interconnected LAN systems. First, a new LAN traffic model is proposed in which correlation of not only packet interarrival times but also packet lengths are considered. An analytic model for a LAN-ATM gateway is next introduced. It employs the dynamic bandwidth control using the proposed LAN traffic model and some performance measures are derived by it. The analytic model takes into account the probability that a bandwidth increase request may be rejected. Finally, some numerical examples are provided using the analysis method and performance comparisons between the dynamic and fixed bandwidth controls are made. As a result, it is quantitatively indicated that () if the equivalent bandwidth is used in average, the dynamic bandwidth control keeps packet and cell loss rates one to two orders lower than the fixed bandwidth control, () when the more strict QOS in terms of loss rate is requested, the dynamic bandwidth control can become more effective.

Asynchronous Transfer Mode (ATM) shared buffer switches have numerous advantages, but have the principal disadvantage that all switch traffic must pass through the bottleneck of a single memory. To achieve the most efficient usage of this bottleneck, the shared buffer is made blockable, resulting in a switch architecture that we call "throttled-buffer", which has several advantageous properties. Shared buffer efficiency is maximized while decreasing both capacity and power requirements. Asynchronous operation is possible, whereby peak link data rates are allowed to approach the aggregate switch rate. Multicasting is also efficiently supported. The architecture and operation of this low-cost switch are described in detail.

We have investigated the relationship between particle removal efficiency and etched depth in SC-1 solution (the mixture composed of ammonium hydroxide, hydrogen peroxide and DI water) for Si wafers. The Si etching rate increases with increasing NH4OH (ammonium hydroxide) concentration. The particle removal efficiency depends on the etched Si depth, and is independent of NH4OH concentration. The minimum required Si etching depth to get over 95% particle removal efficiency is 4 nm. Particles on the Si wafers exponentially decrease with increasing the etched Si depth. However the particle removal efficiency is not affected by particle size ranging from 0.2 to 0.5 µm. The particle removal mechanism on the Si wafers in SC-1 solution is dominated by the lift-off of particles due to Si undercutting and redeposition of the removed particle.

We studied the supply and removal of oil to and from a thin groove and the consequent insertion loss, aiming at matrix optical waveguide switches that utilize optical reflection and transmission effects at the groove. A robot precisely controlled the position of the removal nozzle and the supply needle by a vision servo. The optimum position for the removal nozzle was at the entrance of the groove to a circular oil pool, and the positioning margin was 10-15µm around the optimum position. The on-off ratio of the switching light power at the optimum position was about 30dB. The removal time was proportional to the kinetic viscosity of the oil, and the optimum height of the removal nozzle was independent of the kinetic viscosity of the oil. An analysis of the insertion loss revealed that the main factor in the loss at the reflection is the tilt of the groove wall.

This paper newly estimates the yield suppression for 1.5 V-1 Gbit DRAM caused by threshold voltage variation of MOSFET due to microscopic fluctuations in dopant distributions within the channel region and points out the limitation of the conventional redundancy techniques. The yield suppression is estimated for four main circuit blocks, the memory cell transfer transistor, bit line sense amplifier S/A, I/O line differential amplifier D/A, and the peripheral circuit. It is newly found that for 1.5 V-1 Gbit DRAM due to the effect of the newly estimated threshold voltage variation of MOSFET the bit failures of memory cells become the most dominant failure mode and the failure of D/A which can be ignored for 64 Mbit DRAM level can no longer be neglected. Furthermore, the novel optimized redundancy technique for replacing these failure is described.

A simulation study on cylindrical semiconductor devices is described, where the internal behavior of power devices are analyzed under steady-state condition with considering heat generation. In simulation, circular cylindrical coordinate is used to consider the effect of three-dimensional spreading current flow with keeping calculation time and memory as in two-dimensional simulation. Numerical model is based on the well-known set of Shockley-Roosbroeck semiconductor equations--continuity equations for carriers and Poisson's equation, along with heat flow equation. Drift-diffusion approximation of carrier transport equations is used, taking temperature field as a driving force for carriers into account. Using the cylindrical simulator, numerical analysis of power MOSFETs, which integrate zener diodes to improve the avalanche capability, has been carried out. Results showed that, a parasitic bipolar transistor turns on under forward-biased condition in a power MOSFET with a zener diode. The highest lattice temperature takes place at source edge. Under reverse-biased condition, breakdown occurs at doughnut area around the bottom of source contact (at the upper region of zener junction), and the avalanche current flows detouring the base region of parasitic bipolar transistor which implies that secondary breakdown will be suppressed. The highest lattice temperature region under reverse-biased conditions is the same as the breakdown region. Without zener diodes, on the other hand, breakdown occurs ringing about the edge of source region, and the avalanche current flows through the base region of parasitic bipolar transistor which implies that even MOSFETs may suffer from the secondary breakdown. As channel length becomes short, breakdown caused by punchthrough becomes dominant at the edge of source region.

The aim of this study is to evaluate mental workload (MWL) quantitatively by HRV (Heart Rate Variability) measures. The electrocardiography and the respiration curve were recorded in five different epochs (1) during a rest condition and (2) during mental arithmetic tasks (addition). In the experiment, subjects added two numbers. The work levels (figures of the number in the addition) were set to one figure, two figures, three figures and four figures. The work level had effects on the mean percent correct, the number of answers and the mean processing time. The psychological evaluation on mental workload obtained by the method of paired comparison increased with the work level. Among the statistical HRV measures, the number of peak and trough waves could distinguish between the rest and the mental loading. However, mental workload for each work level was not evaluated quantitatively by the measure. The HRV measures were also calculated from the power spectrum estimated by the autoregressive (AR) model identification. The ratio of the low frequency power to the high frequency power increased linearly with the work level. In conclusion, the HRV measures obtained by the AR power spectrum analysis were found to be sensitive to changes of mental workload.

This paper discusses the design of an ITS to realize a load-oriented tutoring to enhance the student's explanation understanding. In the explanation understanding, it is to be hoped that a student not only memorizes the new information from an explanation, but also relates the acquired information with his/her own knowledge to recognize what it means. This relating process can be viewed as the one in which the student structures his/her knowledge with the explanation. In our ITS, we regard the knowledge-structuring activities as the explanation understanding. In this paper, we propose an explanation, called a load-oriented explanation, with the intention of applying a load to the student's knowledge-structuring activities purposefully. If the proper load is applied, the explanation can induce the student to think by himself/herself. Therefore he/she will have a chance of gaining the deeper understanding. The important point toward the load-oriented explanation generation is to control the load heaviness appropriately, which a student will bear in understanding the explanation. This requires to estimate how an explanation promotes the understanding activities and how much the load is applied to the activities. In order to provide ITS with the estimation, we have built an Explanation Effect Model, EEM for short. Our ITS consists of an explanation planner and a self-explanation environment. The planner generates the load-oriented explanation based on EEM. The system also makes a student explain the explanation understanding process to himself/herself. Such self-explanation is useful to let the student be conscious of the necessity of structuring his/her knowledge with the explanation. The self-explanation environment supports the student's self-explanation. Furthermore, if the student reaches an impasse in self-explaining, the planner can generate the supporting explanation for the impasse.

A simulation-based ITS (Intelligent tutoring system), SRIM, has been developed for the purpose of providing individualized learning to students of PID control. We first indicate that the following two steps will be a burden to the student during personal use of simulators: 1) Selection of operational goals and 2) Interpretation of the simulation results. In order to reduce the burden of students in learning with a simulator, SRIM guides the learning process by providing local goals for PID controller tuning and by giving messages. Two tutoring strategies: i.e. the exercise style strategy and the illustrating style strategy, are employed in SRIM. In the exercise style strategy, a local goal for tuning a PID controller is first given to the student. A local goal is defined as one which can be satisfied by a single operation step such as Decrease the off-set." The student selects his operation and executes the simulation. By observing the simulation, the student understands whether his operation was a success or a failure. The illustrating style strategy is invoked to repair the student's erroneous knowledge when a contradiction is detected in the student model or a wrong operation is selected repeatedly. The architecture of ITS is employed to perform the local goal selection and the tutoring strategy switching, in a natural, well timed manner. The performance of SRIM was evaluated for the purpose of demonstrating the effectiveness of the teaching strategy. The evaluation experiment was carried out in the following steps: 1) Pre-test, 2) Learning and 3) Post-test. The teaching effect of SRIM was compared with other learning methods such as simple use of simulators or a textbook from the results of the pre-test and the post-test. The results showed that SRIM is effective in providing individualized learning with simulators.

In this paper, we present an electronic voting scheme with a single voting center using an anonymous channel. The proposed scheme is a 3-move protocol between each voter and the center, with one extra move if one wants to make objection to the tally. This objection can be broadcasted widely since it will not disclose the vote itself to the other parties besides the center. The main idea in the proposal is that each voter sends anonymously a public key signed by the center and an encrypted vote decryptable using this key. Since even the center cannot modify a received ballot to a different vote using the same public key, the key can be used as an evidence in making open objection to the tally.

Experimental evidence of a two-step enhancement in electromigration lifetime is presented through pulsed testing that extends over a wide frequency range from 7 mHz to 50 MHz. It is also found, through an accompanying failure analysis, that the failure mechanism is not affected by current pulsing. Test samples were the lowew metal lines and the through-holes in double-level interconnects. The same results were obtained for both samples. The testing temperature of the test conductor was determined considering the Joule heating to eliminate errors in lifetime estimation due to temperature errors. A two-step enhancement in lifetime is extracted by normalizing the pulsed electromigration lifetime by the continuous one. The first step occurs in the frequency range from 0.1 to 10 kHz where the lifetime increases with (duty ratio)-2 and the second step occurs above 100 kHz with (duty ratio)-3. The transition frequency in the first-step enhancement shifts to the higher frequency region with a decrease in stress temperature or an increase in current density, whereas the transition frequency in the second step is not affected by these stress conditions. The lifetime enhancement is analyzed in relation to the relaxation process during the current pulsing. According to the two-step behavior, two distinct relaxation times are assumed as opposed to the single relaxation time in other proposed models. The results of the analysis agree with the experimental results for the dependence on the frequency and duty ratio of pulses. The two experimentally derived relaxation times are about 5 s and 1 µs.