A discrete-time neuron model having a refractory period and containing a binary hysteresis output function is introduced. A detailed mathematical analysis of the output response is carried out and the necessary and sufficient condition which a sequence must satisfy in order to be designated as a periodic response of the neuron model under a constant or periodic stimulation is given.

Some problems in formal language theory are considered and are shown to be deterministic exponential time complete. They include the problems for a given context-free grammar G, a nondeterministic finite automaton M, a deterministic pushdown automaton MD, of determining whether L(G)L(M), and whether L(MD)L(M). Polynomial time reductions are presented from the pebble game problem, known to be deterministic exponential time complete, to each of these problems.

An adaptive algorithm is presented for fuzzy clustering of data. Partitioning is fuzzified by addition of an entropy term to objective functions. The proposed method produces more convex membership functions than those given by the fuzzy c-means algorithm.

An accurate numerical solution is presented for the electromagnetic scattering from a double strip grating, where the strip planes are each supported by a dielectric slab. This structure is a model of polarization diplexers. The direction of propagation and the polarization of the incident plane wave are arbitrary. We derive a set of singular integral equations and solve it by the moment method, where the Chebyshev polynomials are successfully used as the basis and the testing functions. By numerical computations we examine the dependence of the diplexing properties on grating parameters in detail. The cross-polarization characteristics at skew incidence are also referred. From these results we construct an algorithm for the design of polarization diplexers.

Robust-fault tolerance is a property that a computational result becomes nearly equal to the correct one at the occurrence of faults in digital system. There are many cases where the safety of digital control systems can be maintained if the property is satisfied. In this paper, robust-fault-tolerant three-valued arithmetic modules such as an adder and a multiplier are proposed. The positive and negative integers are represented by the number of 1's and 1's, respectively. The design concept of the arithmetic modules is that a fault makes linearly additive effect with a small value to the final result. Each arithmetic module consists of identical submodules linearly connected, so that multi-stage structure is formed to generate the final output from the last submodule. Between the input and output digits in the submodule some simple functional relation is satisfied with respect to the number of 1's and 1's. Moreover, the output digit value depends on very small portion of the submodules including the input digits. These properties make the linearly additive effect with a small value to the final result in the arithmetic modules even if multiple faults are occurred at the input and output of any gates in the submodules. Not only direct three-valued representation but also the use of three-valued logic circuits is inherently suitable for efficient implementation of the arithmetic VLSI system. The evaluation of the robust-fault-tolerant three-valued arithmetic modules is done with regard to the chip size and the speed using the standard CMOS design rule. As a result, it is made clear that the chip size can be greatly reduced.

The main interest of this paper is the theoretical analysis of a recursive periodically time varying digital filter. The generalized transfer function of a recursive periodically time varying digital filter was obtained from its difference equation. It was proved that by making use of the generalized transfer function, we can not only derive the input and output relationship of a recursive periodically time varying digital filter easily but also obtain its equivalent structure effectively. An interesting property of a recursive periodically time varying digital filter was also derived by making use of its generalized transfer function. Moreover, it was completed in this paper the investigation of the generalized transfer functions and impulse responses of other periodically time varying models, including an input sampling polyphase model and an output sampling polyphase model. Meanwhile, the multirate Quadrature Mirror Filter bank system was proved by the authors to be a periodically time varying system. Several examples were also provided to illustrate the effectiveness of using the generalized transfer function to obtain the equivalent structure of a recursive periodically time varying digital filter.

In this paper, two models for associative memory based on a measure of manhattan length are proposed. First, we propose the two-layered model which has an advantage to its implementation by using PDN. We also refer to the way to improve the recalling ability of this model against noisy input patterns. Secondly, we propose the other model which always recalls the nearest memory pattern in a measure of manhattan length by lateral inhibition. Even if a noise of input pattern is so large that the first model can not recall, this model can recall correctly against such a noisy pattern. We also confirm the performance of the two models by computer simulations.

Global dynamic behavior particularly the bifurcation of periodic orbits of a parallel blower system is studied using a piecewise linear model and the one-dimensional map defined by the Poincare map. First several analytical tools are presented to numerically study the bifurcation process particularly the bifurcation point of the fixed point of the Poincare map. Using two bifurcation diagrams and a bifurcation set, it is shown how periodic orbits bifurcate and leads to chaotic state. It is also shown that the homoclinic bifurcations occur in some parameter regions and that the Li & Yorke conditions of the chaotic state hold in the parameter region which is included in the one where the homoclinic bifurcation occurs. Together with the above, the stable and unstable manifolds of a saddle closed orbit is illustrated and the existence of the homoclinic points is shown.

A further study on a VLSI system compiler, named VEGA (VLSI Embodiment for General Algorithms), is presented. It maps a general digital signal processing algorithm onto a neo-systolic array, which is a VLSI oriented multiprocessor array. Highly complicated mapping problem is divided into subproblems such as modularization, operation grouping, processor placement, scheduling, control logic synthesis, and mask pattern generation. In this paper, the modularization technique is proposed which homogenizes all the operations of the processing algorithm to multiply-add operations. The processor placement algorithm to map processing algorithm onto a neo-systolic array so as to minimize data transfer time is also proposed.

Although the perception of gloss is based on human visual perception, some methods for measuring glossiness, in contrast to human ability, have been proposed involving plane surfaces. Glossiness defined in these methods, however, does not correspond with psychological glossiness perceived by the human eye over the wide range from relatively low gloss to high gloss. In addition, the change in the incident angle causes a deviation in the measurement of glossiness. A new method for measuring glossiness is proposed in this study. For the new definition of glossiness Gd, the brightness function is utilized. We also extract the value of smoothness of the object's surfaces for use as a factor of glossiness. The measuring equipment consists of a light source, an optical system and a personal computer. Glossiness Gd of paper and plastics is measured with the use of this equipment. In all samples, a strong correlation, with a correlation coefficient of more than 0.97, has been observed between Gd and psychological glossiness Gph. The variance of measured glossiness due to the change in the incident angle of light is small in comparison with that of conventional methods. Based on these findings, it has been found that this method is useful for measuring glossiness of plane objects in the range from relatively low gloss to high gloss.

Rapid advances in integrated circuit technology based on binary logic have made possible the fabrication of digital circuits or digital VLSI systems with not only a very large number of devices on a single chip or wafer, but also high-speed processing capability. However, the advance of processing speeds and improvement in cost/performance ratio based on conventional binary logic will not always continue unabated in submicron geometry. Submicron integrated circuits can handle multiple-valued signals at high speed rather than binary signals, especially at data communication level because of the reduced interconnections. The use of nonbinary logic or discrete-analog signal processing will not be out of the question if the multiple-valued hardware algorithms are developed for fast parallel operations. Moreover, in VLSI or ULSI processors the delay time due to global communications between functional modules or chips instead of each functional module itself is the most important factors to determine the total performance. Locally computable hardware implementation and new parallel hardware algorithms natural to multiple-valued data representation and circuit technologies are the key properties to develop VLSI processors in submicron geometry. As a result, multiple-valued VLSI processors make it possible to improve the effective chip density together with the processing speed significantly. In this paper, we summarize several potential advantages of multiple-valued VLSI processors in submicron geometry due to great reduction of interconnection and due to the suitability to locally computable hardware implementation, and demonstrate that some examples of special-purpose multiple-valued VLSI processors, which are a signed-digit arithmetic VLSI processor, a residue arithmetic VLSI processor and a matching VLSI processor can achieve higher performance for real-world computing system.

This paper presents a VLSI-oriented arithmetic design method using a radix-2 redundant number representation with digit set {0, 1, 2} and multiple-valued current-mode (MVCM) circuit technology. We propose a carry-propagation-free (CPF) parallel addition method with redundant digit set {0, 1, 2} which is suitable for the design with MVCM circuits. Several types of CPF parallel adders are compared and the proposed CPF parallel adder with MVCM circuits offers the best total performance with respect to speed, complexity, and power dissipation. The designed basic arithmetic circuits has sufficient noise immunity to the supply voltage fluctuation which is important for stable operations of the VLSI circuits. The CPF parallel adder is effectively used as the reduction scheme of partial products in a high-speed compact multiplier. For example, the designed 3232 bit multiplier reduces the number of active elements to two-third and the number of interconnections to one-fifth of the corresponding binary Wallace tree multiplier, where the speed is almost the same. The structure is simple and regular. The static power dissipation of the designed 32-bit multiplier is estimated to be the mean value of 212 mW and the worst case of 708 mW. The total power including dynamic power dissipation would not be so large compared with that of the 32-bit binary CMOS multiplier reported under 10 MHz operation.

In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

We are presenting a high-speed MOS multiplier and divider, which is based on a redundant binary representation (using the digits 1, 0, 1), and their implementation in a 64-bit RISC microprocessor. The multiplier uses a redundant binary adaptation of the Booth algorithm and a redundant binary adder tree. We compared it to a multiplier using a two bit version of the Booth algorithm and a Wallace tree and found that the former multiplier is useful in VLSI because of its high-speed operation, small number of transistors, and good regularity. We also found that the divider performed by Newton's iteration using the multiplier is useful in VLSI. Implementing the multiplier and divider in a highly integrated 64-bit RISC microprocessor, we obtained a high-speed microprocessor.

The demand for high-speed image processing is obvious in many real-world computations such as robot vision. Not only high throughput but also small latency becomes an important factor of the performance, because of the requirement of frequent visual feedback. In this paper, a high-performance VLSI image processor based on the multiple-valued residue arithmetic circuit is proposed for such applications. Parallelism is hierarchically used to realize the high-performance VLSI image processor. First, spatially parallel architecture that is different from pipeline architecture is considered to reduce the latency. Secondly, residue number arithmetic is introduced. In the residue number arithmetic, data communication between the mod mi arithmetic units is not necessary, so that multiple mod mi arithmetic units can be completely separated to different chips. Therefore, a number of mod mi multiply adders can be implemented on a single VLSI chip based on the modulus-slice concept. Finally, each mod mi arithmetic unit can be effectively implemented in parallel structure using the concept of a pseudoprimitive root and the multiple-valued current-mode circuit technology. Thus, it is made clear that the throughout use of parallelism makes the latency 1/3 in comparison with the ordinary binary implementation.

An adder-based arithmetic VLSI processor using the SD number system is proposed for the applications of real-time computation such as intelligent robot system. Especially in the intelligent robot control system, not only high throughput but also small latency is a very important subject to make quick response for the sensor feedback situation, because the next input sample is obtained only after the robot actually moves. It is essential in the VLSI architecture for the intelligent robot system to make the latency as small as possible. The use of parallelism is an effective approach to reduce the latency. To meet the requirement, an architecture of a new multiple-valued arithmetic VLSI processor is developed. In the processor, addition and subtraction are performed by using the single adderbased processing element (PE). More complex basic arithmetic operations such as multiplication and division are performed by the appropriate data communications between the adder-based PEs with preserving their parallelism. In the proposed architecture, fine-grain parallel processing at the adder-based PE level is realized, and all the PEs can be fully utilized for any parallel arithmetic operations according to adder-based data dependency graph. As a result, the processing speed will be greatly increased in comparison with the conventional parallel processors having the different kinds of the arithmetic PEs such as an adder, a multiplier and a divider. To realize the arithmetic VLSI processor using the adder-based PEs, we introduce the signed-digit (SD) number system for the parallel arithmetic operations because the SD arithmetic has the advantage of modularity as well as parallelism. The multiple-valued bidirectional currentmode technology is also used for the implementation of the compact and high-speed adder-based PE, and the reduction of the number of the interconnections. It is demonstrated that these advantges of the multiple-valued technology are fully used for the implementation of the arithmetic VLSI processor. As a result, the latency of the proposed multiple-valued processor is reduced to 25% that of the binary processor integrated in the same chip size.

A technique is presented for constructing (d,k) block codes capable of detecting single bit errors and single peak-shift errors in consecutive two runs. This constrains the runlengths in the code sequences to odd numbers. The capacities and the cardinalities for finite code length of these codes are described. A technique is also proposed for constructing (d,k) block codes capable of correcting single peak-shift errors.

Two computational-geometric approaches to linear programming are surveyed. One is based on the prune-and-search paradigm and the other utilizes randomization. These two techniques are quite useful to solve geometric problems efficiently, and have many other applications, some of which are also mentioned.

The evolution of Multiple-Valued Logic (MVL) circuits has been inexorably tied to the rapid technological changes induced by evolving needs and emerging developments in computing methodologies. Unfortunately for MVL, the numbers of designers of technologies and circuits whose lives are dedicated to the improvement of binary techniques, are large and overwhelming. Correspondingly, technological developments in MVL typically await the appearance of a problem or technique in the larger binary world to motivate and/or make possible some new advance. Such opportunities are inevitably quite transient since each such problem is simultaneously attacked by many others of a more conventional bent, and, as well, each technological change begets yet another, quickly. It is in the sensing of this reality that the present paper is written. Correspondingly, its thrust is two-fold: One target is the possibility of encouraging a leap ahead through modest technological projection. The other is the possibility of identifying application areas that already exist in this unbalanced competition, but which are specially suited to multiple-valued solutions. For example, it has been clear for decades that one such area is that of arithmetic. Correspondingly, we in MVL must strive quickly to concentrate our efforts on applications that exploit such demonstrable strengths. Some such applications are includes here; others are visible historically, many probably remain to be found: Search on!