A 0.4 µm stacked gate cell for a 64 Mbit flash memory has been developed which has the Symmetrical Side Wall Diffusion Self Aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p+ pockets at both the drain and the source, and adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the channel erasing scheme applying negative bias to the gate, which is adopted for the SSW-DSA cell, shows lower trapped charges after Write/Erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance an retention characteristics than conventional erasing schemes.

The pressure waveforms indicated on a catheter manometer system are subject to serious distortion due to the resonance of the catheter itself, or the compliance of a particular transducer. Although several methods have been proposed for improving those characteristics, they ahave never been put into practice. We have focused on the transfer function of the catheter manometer, and made a pilot system, using the natural observation method. This method has been suggested as a means of studying the structure of the instantaneous waveform. In this manner, we were able to increace the bandwidth in the ferquency domain and reduce the ringing in the time domain. Correction was performed automatically, using a step wave. Reproduction of the waveform with a flushing device, was a task of equal simplicity, that allowed us to estimate the system parameters so that the response waveform became step-like. In the experiment, our system provided distortion-free left-ventricular pressure waveform measurements and exact evaluation of the cardiac pumping system. The values obtained came much closer to the original figures arrived at by the catheter-tip manometer system.

This paper describes a nonstationary spectral analysis method and its application to prognosis and diagnosis of automobiles. An instantaneous frequency spectrum is considered first at a single point of time based on the instantaneous representation of autocorrelation. The spectral distortion is then considered on two-dimensional spectrum, and the filtering is introduced into the instantaneous autocorrelations. By the above procedure, the Instantaneous Covariance method (ICOV), the Instantaneous Maximum Entropy Method (IMEM), and the Wigner method are shown and they are unified. The IMEM is used for the time-dependent spectral estimation of vibration and acoustic sound signals of automobiles. A multi-dimensional (M-D) space is composed based on the variables which are obtained by the IMEM. The M-D space is transformed into a simple two-dimensional (2-D) plane by a projection matrix chosen by the experiments. The proposed method is confirmed useful to analyze nonstationary signals, and it is expected to implement automatic supervising, prognosis and diagnosis for a traffic system.

This paper describes a new timing calibration method for IC testers that uses a Timing Calibration Device (TCD). The TCD is a chip fabricated using the same process the device to be tested. Since the TCD has the same assignment pins as the LSI memory device under test (called the "MUT"), it enables an IC tester to evaluate the timing accuracy at the input/output terminal of MUT. The block-select-access time of a 1 K ECL RAM, which is less than 3.0 nanoseconds, has been accurately measured using this device. A timing-calibration subsystem is proposed for IC testers as an application of the TCD. Such a device would achieve precise measurement of high-speed LSI memory devices.

The process of room acoustic planning & design can be aided by Binaural Technology. To this end, a three-stage modelling process is proposed that consists of a "sound"-specification phase, a design phase and a work-plan phase. Binaural recording, reproduction and room simulation techniques are used throughout the three phases allowing for subjective/objective specification and surveillance of the design goals. The binaural room simulation techniques involved include physical scale models and computer models of different complexity. Some basics of binaural computer modelling of room acoustics are described and an implementation example is given. Further the general structure of a software system that tries to model important features of the psychophysics of binaural interaction is reported. The modules of the model are: outer-ear simulation, middle-ear simulation, inner-ear simulation, binaural processors, and the final evaluation stage. Using this model various phenomena of sound localization and spatial hearing, such as lateralization, multiple-image phenomena, summing localization, the precedence effect, and auditory spaciousness, can be simulated. Finally, an interesting application of Binaural Technology is presented, namely, a so called Cocktail-Party-Processor. This processor uses the predescribed binaural model to estimate signal parameters of a desired signal which may be distored by any type of interfering signals. In using this strategy, the system is able to even separate the signals of competitive speakers.

The self-checking design using 2-rail logic is one of the most popular design of self-shecking circuits. Even for a self-checking circuit, a test is necessary after VLSI chip or system fabrication, at each time the system is powered, and, under certain circumstances, in the case of maintenance. Therefore, an easy test scheme is desirable for that circuit. A new design method for a 2-rail logic combinational circuit is proposed, where stuck-open and sutck-on faults FETs can be easily detected. In the proposed circuit design, 4 FETs are added to each gate in a conventional 2-rail logic circuit. Two logical gates, DOR and DAND, are also added to the circuit as fault observing gates. Each test consists of a sequence of 3 input vectors, that is, a type of 3-pattern test, ti1ti2ti3. A test can be easily generated and fault observation is easy. Stuck-at fault and stuck-open fault on lines and almost all multiple faults can also be detected by the test. A gate construction method, test generation method, circuit construction method, and several discussions including gate delay increasing are presented.

Fahlman and Lebiere's (FL) learning algorithm begins with a two-layer network and in course of training, can construct various network architectures. We applied FL algorithm to the same three-layer network architecture as a back propagation (BP) network and compared their generalization properties. Simulation results show that FL algorithm yields excellent saturation of hidden units which can not be achieved by BP algorithm and furthermore, has more desirable generalization ability than that of BP algorithm.

This paper describes a new method for verifying designs at the RTL with respect to their specifications at the functional level. The base of the verification method shown here is the translation of the specification and design representations to graph models, where the descriptions common to both representations have a symbolic representation. These symbol labeled graphs are then simplified and, by solving the all node-pair path expression problem for them, a pair of regular expressions is obtained for every two nodes in the graphs. The first regular expression in each pair represents the flow of control and the second one the flow of data between the corresponding nodes. The process of verification is carried out by checking whether or not every pair of regular expressions of the specification has a corresponding pair in the design.

This paper describes configuration and operation of a high-frequency link resonant inverter using cycloconverter techniques. In this inverter, a resonant link high-frequency voltage generated in a primary resonant inverter is isolated by a high-frequency transformer, then directly converted into a resonant link low-frequency voltage in a cycloconverter. The switching losses and surge voltage levels can be reduced by making all switches in the primary inverter and the cycloconverter operate at zero voltage. The relationship between characteristic impedance of the resonant circuit and the conversion efficiency, and the distortion factor characteristics of the output voltage waveforms are discussed by comparing of analytical and experimental results.

This paper describes the superior performances of the NAND EEPROM. Those are 1) a very small cell area: 4.83 µm2 using 0.7 µm design rule, 2) small block size for erasing: 4 Kbyte block erasing for 4 M-bit NAND EEPROM, 3) high speed programming: 180 nsec per byte for 4 M-bit NAND EEPROM, 4) large number of erase/program endurance cycles: more than 105 cycles for 4 M-bit NAND EEPROM. These extended performances coincide with the requirement for the EEPROM to replace magnetic memories such as hard and floppy disks. Especially, it is shown that NAND EEPROM has the capability to enlarge the erase/program endurance up to 3.6108 cycles. This endurance is a result of the erase and program mechanism of the NAND EEPROM cell. Fowler-Nordheim (F-N) tunneling currents flow from the substrate to the floating gate during programming and opposite currents flow during erasing. This bi-polarity F-N tunneling erase/program operation extends the life time of the tunnel oxide which results in an improved endurance.

This paper presents a new type of zero-voltage-switched (ZVS) push-pull dc-dc converter with two synchronous rectifiers in the secondary circuit. ZVS is realized using the magnetizing current of the transformer as a constant current source during the commutation. The output voltage is controlled by PWM with a constant switching frequency. The circuit operation is described using equivalent circuits. The steady-state and dynamic characteristics are analyzed and confirmed experimentally.

The paper considers the design of two families of binary block codes developed for controlling large numbers of errors which may occur in LSI, optical disks and other devices. The semidistance codes are capable of assuring a required signal-to-noise ratio in information retrieval; the t-symmetric error correcting/all unidirectional error detecting" (t-SyEC/AUED) codes are capable of correcting t or fewer symmetric errors and also detecting any number of unidirectional errors caused by the asymmetric nature of transmission or storage madia. The paper establishes an equivalence between these families of codes, and proposes improved methods for constructing, for any values of t, a class of nonsystematic constant weight codes as well as a class of systematic codes. The constructed codes of both classes are shown to be optimal when t is O, and of asymptotically optimal order" in general cases. The number of redundant bits of the obtained nonsystematic code is of the order of (t+1/2)log2 K bits, where K is the amount of information encoded. The obtained systematic codes have redundancy of the order of (t+1)log2 K bits.

This paper describes a novel Recessed Stacked Capacitor (RSTC) structure for 256 Mbit DRAMs, which can realize the requirements for both fine-pattern delineation with limited depth of focus and high cell capacitance. New technologies involved are the RSTC process, 0.25 µm phase-shift lithography and CVD-tungsten plate technology. An experimental memory array has been fabricated with the above technologies and 25 fF/cell capacitance is obtained for the first time in a 0.61.2 µm2 (0.72 µm2) cell.

An efficient reconstruction algorithm for diffraction tomography based on the modified Newton-Kantorovich method is presented and numerically studies. With the Fréchet derivative obtained for the Helmholtz equation, one can derive an iterative formula for getting an object function, which is a function of refractive index of a scatterer. Setting an initial guess of the object function to zero, the pth estimate of the function is obtained by performing the inverse Fourier transform of its spectrum. Since the spectrum is bandlimited within a low-frequency band, the algorithm does not require usual regularization techniques to circumvent ill-posedness of the problem. For numerical calculation of the direct scattering problem, the moment method and the FFT-CG method are utilized. Computer simulations are made for lossless and homogeneous dielectric circular cylinders of various radii and refractive indices. In the iteration process of image reconstruction, the imaginary part of the object function is set to zero with a priori knowledge of the lossless scatterer. Then the convergence behavior of the algorithm remarkably gets improved. From the simulated results, it is seen that the algorithm provides high-quality reconstructed images even for cases where the first-order Born approximation breaks down. Furthermore, the results demonstrate fast convergence properties of the iterative procedure. In particular, we can successfully reconstruct the cylinder of radius 1 wavelength and refractive index that differs by 10% from the surrounding medium. The proposed algorithm is also effective for an object of larger radius.

The newly developed GaAs-pin/SLM, that is structured with a GaAs-pin diode photodetector and a ferroelectric liquid crystal as the light phase modulator, shows the accumulative thresholding characteristic against the optical energy of the write-in pulse train. We experimentally investigate this characteristic and discuss its applications to optical parallel processings.

This paper proposes a new fault tolerant intercommunication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed intercommunication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in a processing element of the system. In addition, it can overcome conventional problems caused in interconnection circuits to flow data with one way direction such as a pipeline processing.

To improve the stability and the power supply rejection ratio (PSRR) of the voltage limiter circuit used in high-density DRAM's we present a voltage limiter circuit with pole-zero compensation. Analytical expressions that describe the stability of the circuit are provided for comprehensive consideration of circuit design. Voltage limiters with pole-zero compensation are shown to have excellent performance with respect to the stability, PSRR, and circuit area occupation. The parasitic resistances in internal voltage supply lines, signal transmission lines, and transistors are important parameters determining the stability of pole-zero compensation. Evaluation of a 16-Mbit test device revealed internal voltage fluctuations of 6% during operation of a chip-internal circuit, a phase margin of 53, and a PSRR of 30 dB.

A new circuit and a transformer structure is described for a high-input-voltage converter operating at a high switching frequency. The two-MOSFET forward converter is suitable for a high-input-voltage converter. To increase the switching frequency, the reset period of the transformer core flux must be reduced. There are a few methods for decreasing the reset period. Increasing the transformer flyback voltage and reducing its stray capacitance are effective in decreasing the reset period without increasing power loss. A new two-MOSFET forward converter is proposed which uset the increased flyback voltage and a transformer structure to reduce the stray capacitance. The new converter using this transformer provides the basis for a 48-V, 100-W output, 270-V input converter operating at 200kHz with high efficiency (above 95%).

The characteristics of voltage-resonant dc-dc converters have already been analyzed and described. However, in the conventional analysis, the inductance of the reactor is assumed to be infinity and the loss resistance of the power circuit is not taken into account. Also, in some cases, the averaging method is applied to analyze the resonant dc-dc converters as well as the pwm dc-dc converters. Consequently, the results from conventional analysis are not entirely in agreement with the experimental ones. This paper presents a general design-oriented analysis of the buck-boost type voltage-resonant dc-dc converter in the continuous and discontinuous modes of the reactor current. In this analysis, the loss resistance in each part of the power circuit, the inductance of the reactor, the effective value (not mean value) of the power loss, and the energy-balance among the input, output and internal-loss powers are taken into account. As a result, the behavior and characteristics of the buck-boost type voltage-resonant dc-dc converter are fully explained. It is also revealed that there is a useful mode in the discontinuous reactor current region, in which the output voltage can be regulated sufficiently for the load change from no load to full load and for the relatively large change of the input voltage, and then the change in the switching frequency can be kept relatively small.

There have been few studies on formal approaches to the specification and realization of asynchronous sequential circuits. For synchronous sequential circuits, an algebraic method is proposed as one of such approaches, but it cannot be applied to asynchronous ones directly. This paper describes an algebraic method of specifying the abstract behavior of asynchronous sequential circuits. We select an daisy chain arbiter as an example of them. In the arbiter, state transitions are caused by input changes, and all the modules do not always make state transitions simultaneously. These are main obstacles to specify it in the same way as sychronous sequential circuits. In order to remove them, we modify the meaning of input in specifications and introduce pseudo state transitions so that we can regard all the modules as if they make state transitions simultaneously. This method can be applied to most of the other asynchronous sequential circuits.