In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. Our interest is on simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. Conventional logic simulation based on min/max delay model leads to over-pessimistic results. In our new method, the cases of possible delay values of each gate are encoded by binary vectors. The circuit behavior for all the possible combinations of the delay values are simulated based on symbolic simulation by assigning Boolean variables to the binary vectors. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using shared binary decision diagrams (SBDD's) as internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.

Stochastic Petri Nets and Generalized Stochastic Petri Nets as well as other extensions to Stochastic Petri Nets have been widely applied as a model of asynchronous concurrent process, or as an aid to analyze or design concurrent systems. This paper presents an Extended Stochastic Petri Net model for a shift processing system in which three kinds of sink may occur and an arbitrary time distribution is incorporated, provides an analytical method based on a Markov renewal process with some non-regeneration points to clarify the probabilistic behavior of the system, and finally evaluates the performance of the system with numerical values.

A design system for a special purpose processor executing algorithms described by high level language is discussed. The system can generate an optimized architecture for the processor and also supply a specialized high level language compiler for the processor. A new optimization procedure is introduced to find effective functional blocks that can contribute to the improvement of performance. Functional blocks are found by simulation of the frequently appearing patterns of execution in the algorithm and used to yield a useful combined instruction.

This paper presents unique specification environments for LOTOS, which is one of FDTs (Formal Description Techniques) developed in ISO. We first discuss the large gap in terms of syntax and semantics between informal specifications at the early stage of specification design and formal specifications based on FDT such as LOTOS. This large gap has been bridged by human intelligent works thus far. In order to bridge the large gap, we have designed user-friendly specification environments for FDTs. The outlines of SEGL (Specification Environment for G-LOTOS), CBP (Concept-Based Programming environment) and MBP (Model-Based Programming environment) are described. The effectiveness of software development under such an environment is demonstrated using application examples from OSI and non-OSI protocols.

Recently, Burch et al. proposed symbolic model checking method to verify sequential machines formally. The method, which is based on logic function manipulation using binary decision diagram, can handle large sequential machines that cannot be handled by the conventional techniques. The expressive power of Computational Tree Logic (CTL), which was used by Burch et al., is not very powerful, for example, CTL cannot describe repetition of events. This papers shows an extension of the symbolic model checking algorithm to Branching time regular temporal logic (BRTL), which has been proposed by the authors as an improvement of CTL in terms of expressive power. The implemented verifier based on the proposed algorithm could verify behaviors of a microprocessor composed of approximately 1,600 gates and 68 flipflops.

This paper describes a new method for designing switching software called DDL (Data Driven Logic). The new design method adopts the dataflow concept and graphical programming using a dataflow diagram. A dataflow diagram is used for software representation, and a dataflow mechanism is emulated on a conventional von Neumann processor. The DDL method has the following advantages; (1) general advantages of dataflow software; i.e. easily understandable programs using graphical representations, and easy description of parallelism, (2) modular design using reusable software components, (3) easy design and programming with a graphical user interface. This paper presents the general concepts and structure of DDL. It also discusses the dataflow emulation mechanism, the DDL software development process, the DDL programming environment, an evaluation of the DDL call processing program applied to a commercial PABX, and some unsolved problems of DDL.

The mechanisms for executing concurrent applications proposed so far fall into one of three groups: processes, kernel-level threads, and user-level threads. Each of them is insufficient in terms of either parallelism, the flexibility to combine separately developed programs at run-time, or costs of operations such as creation, switching, and termination. A thread facility in the XERO operating system overcomes this problem and provides a uniform framework for executing concurrent applications. To achieve parallelism of threads, the flexibility to combine separately developed programs at run-time, and fast thread operations, the operating system kernel and a thread management module in a user address space manage threads cooperatively. We implemented the cooperative thread management mechanism and measured its performance to examine the effectiveness of our approach.

This paper describes the integration of a qualitative method and a quantitative method by Bottleneck Diagnosis/Improvement Expert Systems for Synchronized queueing network (BDES-S and BIES-S). On the basis of qualitative reasoning, BDES-S can carry out parameter tuning in order to diagnose and improve bottlenecks of synchronized queueing networks. BDES-S can produce several alternative qualitative improvement plans for one bottleneck server. BIES-S can produce quantitative improvement equations for each qualitative improvement plan. Our method using BDES-S and BIES-S can integrate both quantitative and qualitative methods for parameter tuning on complicated queueing synchronized networks.

Relational query languages like SQL and QUEL require the users to understand the complex detabase structure. This is a burden on end users, especially novice end users who access the database on a casual and infrequent basis. To alleviate the need to know the logical database origanization, this paper proposes the use of a semantic data model, known as the Enhanced Entity-Relationship (EER) model, as a front-end to the relational systems. A formal, high-level Visual Knowledge Query Language (VKQL) has also been designed for this interface. This language provides for knowledge abstraction as the user communicates only domain knowledge with the system without any implication on the storage structure or search strategies. A translation algorithm is also described in this paper to translate VKQL queries to Standard SQL equivalents.

It is well known that the multiple-valued signed-digit (SD) arithmetic circuits have the attractive features of compactness and high-speed operation. However, both of these features have yet to be utilized fully. In this paper, we consider the application of a parallel-structure-based VLSI processor. A high-performance parallel-structure-based multiple-valued VLSI processor using the radix-2 SD number system is proposed. Its compactness makes the parallelism high under chip size limitations in comparison with the ordinary binary arithmetic circuits. Moreover, the speed of the single arithmetic module is very high in the SD arithmetic circuits, so that we can take advantage of the high-speed operation in the parallel-structure-based VLSI processor chip. The multiple-valued bidirectional current-mode technology is used not only in high-speed small sized arithmetic circuits, but also in reducing the number of connections in the parallel-structure-based VLSI processor. The proposed processor is specially developed for real-time digital control, where the performance is evaluated by delay time. Performance estimation using SPICE simulators shows that the delay time of proposed processor for matrix operations such as matrix multiplication is greatly reduced in comparison with a conventional binary processor.

In case of the system identification problem, such as an echo canceller, estimated impulse response obtained by the frequency-domain adaptive filter based on the circular convolution has estimation error because the unknown system is based on the linear convolution in the time domain. In this correspondence, we consider a sufficient condition to reduce the estimation error.

Runlength-limited block codes are investigated. These codes are useful for storing data in storage devices. Since most devices are not noiselss, the codes are often required to have some error-control capability. We consider runlength-limited codes that can correct or detect unidirectional byte errors. Some constructions of such codes are presented.

Recently most of the singularities of the equivalent edge currents for flat plates were eliminated by the authors using the paths of most rapid phase variation. A unique direction on the plate was determined for given incidence and observer. This paper extends this method for arbitrary angle wedges and presents the new expressions of the equivalent edge currents. The resultant expressions are valid for any incidence and observation aspects and have no false singularities. Diffraction patterns and radar cross sections of 3-D objects composed of wedges are calculated by using these currents. They show good agreements with experimental data or the results by the other methods.

Analysis of the propagation of circularly symmetric fields is made using the finite-difference beam-propagation method. After testing the accuracy of this method, we analyze the guided-mode transmission of connected fibers whose core radii are different. The propagation behavior of the unguided-mode field generated at the junction is revealed using a transparent boundary condition.

Diffusion of phosphorus impurities from a polycrystalline silicon films into a silicon substrate was investigated as a function of the mean concentration of phosphorus in a polycrystalline silicon film at the first diffusion stage. We presented that good control of the redistribution of implanted phosphorus impurities was possible by optimizing the normalized dose, which is the value: [the total dose of phosphorus impurities]/[the polycrystalline silicon film thickness], in the case of samples both with and without an arsenic doped layers. In the range where the normalized dose was less than 1.52.51020 cm-3, deeper junctions were formed in samples with an arsenic doped layer. In the range where the normalized dose was more than 1.52.51020 cm-3, however, deeper junctions were formed in samples without any arsenic doped layer rather than in samples with an arsenic doped layer. These results mean that formation of the junction in the device structure where a high concentration phosphorus doped polysilicon layer is stacked on to the high concentration arsenic layer embeded at the surface of the substrate can be restricted by optimizing the normalized dose. Moreover, a trade-off relationship between suppressing phosphorus diffusion and maintaining low contact resistance against normalized doses was also observed.

The quality of polycrystalline silicon films and electrical characteristics of polycrystalline silicon gate metal-oxide-semiconductor (MOS) capacitors were investigated under various processing conditions, including phosphorus doping. The stresses observed in Si films deposited in the amorphous phase show complex behavior during thermal treatment. The stresses in as-deposited Si films are compressive. They change to tensile with annealing at 800, and to compressive after an additional annealing at 900. The kind of charges trapped in the SiO2 film during the negative constant current stress in Polycrystalline silicon gate MOS capacitors differ with the maximum process temperature. The trapped charges of samples annealed at 800 were negative, while those of samples annealed at 900 were positive.

It often occurs in the acoustic environment that a specific signal is contaminated by the additional noise of non-Gaussian distribution type. In order to extract exactly the various statistical information of only specific signal from the observed noisy data, a stochastic signal processing by use of digital computer is essential. In this study, a stochastic method for estimating the probability function of the specific signal embedded in the additional noise is first theoretically proposed in a suitable form for the quantized level observation. Then, the effectiveness of the proposed method is experimentally confirmed by applying it to the observed data in the acoustic environment.

In this paper, a type hybrid ARQ scheme with Adaptive Forward Error Correction (ARQ/AFEC) using BCH codes is proposed and analyzed. The basic idea in the proposed type hybrid ARQ/AFEC scheme is to increase the error-correcting capability of BCH code according to channel state using incremental redundancy. The incremental redundancy is the remainder ai(x) of an information frame f(x) of length n divided by a minimum polynomial mi(x) of α2i-1, where α is a primitive element of finite field GF(2l). Let gi(x) be the product of mj(x) (j=1, 2, , i) and let ci(x) be the remainder of f(x) divided by gi(x). The polynomial ci(x) is obtained from the remainders ai(x) and ci-1(x) since mi(x)and gi-1 (x) are relatively prime. Since f(x) + ci(x) is divided by gi(x), f(x) + ci(x) is the codeword of an i-error-correcting BCH code when n2l-1. So, the errors less than or equal to i bits in f(x) can be corrected if ci(x) has no error.

The characteristics of an optical functional integrated circuit and its applications are discussed. This circuit is based upon a Mach-Zehnder interferometer type waveguide device employing thermo-optic effect. This circuit is compact, cost-effective and practical. One proposed application is an optical loopback circuit to test both OCU loop 1 and DSU loop C. This optical loopback circuit with an attenuator and space switches is formed on a common silicon substrate, and using this circuit both loopback and line tests are independently available at the same access point. The other is an optical selector. This optical selector with WDM-MUX/DMUX and space switches is formed on a common silicon substrate, and using this selector, wavelength selection from medium density WDM (MDWDM) signal can be performed. Each MDWDM signal carries both AM and FM-FDM video signals modulated by Subcarrier Multiplexing (SCM) techniques. This selector can be wired in point-to-multipoint configurations to home video appliances.

The effect of mesage-class dependent threshold-type scheduling on queueing delay and resequencing delay for the M/M/n queueing system is analyzed. We first derive the expressions for the state transition equations, mean queueing delay, resequencing delay and total delay for the M/M/n queueing system shared by C different message classes under a threshold-type scheduling in which the threshold values depend on the message class at the head of queue and the number of messages in the buffer. Next, the numerical calculation and the computer simulation are carried out for the queueing system with two servers. It is found that the message-class dependent threshold-type scheduling is effective to reduce the resequencing delay of some specific message class, which can not be attained under the conventional threshold-type scheduling, and thus, the proposed scheduling can satisfy the different requirements of the different message classes, such as minimizing only queueing delay or total delay including resequencing delay.