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22621-22640hit(22683hit)

  • Distributed Signal Transmission System Using Discrete Fourier Transform for High Noise Immunity

    Hyunkoo KANG  Yoon UH  Tasuku TAKAGI  

     
    PAPER

      Vol:
    E75-B No:3
      Page(s):
    188-192

    We propose a new distributed signal (analog or digital) transmission system which has the immunity against the noisy channel. An information signal in transmitter is distributed by distributor and the distributed signal is transmitted. Received signal is reconstructed by the inverse distributor in receiver. In this system, an impulsive interference noise which disturbs the transmission signal in the channel passes decoder only, and this interference noise is distributed by the inverse distributor while the transmitted signal is reconstructed. Some appended signals make it possible to estimate the noise components which inversely distributed with the Fourier transformation as the distributor. Basing upon this principle, the transmission system will have an ability to suppress the impulsive interference, and the channel will have high noise immunity. The construction of receiver which can eliminate the impulsive noise is derived.

  • Modular Expandable Multi-Stage ATM Cross-Connect System Architecture for ATM Broadband Networks

    Satoru OKAMOTO  

     
    PAPER-Switching and Communication Processing

      Vol:
    E75-B No:3
      Page(s):
    207-216

    ATM cross-connect systems, which will be used for provisioning virtual paths (i.e. logical direct connections between exchanges) in future broadband transport networks, simplify network configuration and yield increased routing and capacity allocating flexibility. This paper describes the design of a large capacity ATM cross-connect system that has a multi-stage network structure which requires only one type of switch module. The capacity of the proposed system can be easily increased without service interruptions. To realize cell sequence integrity, a time stamp is added to the self-routing tag. Required time stamp length and efficient module size are discussed.

  • A Simple Hyperchaos Generator Including One Ideal Diode

    Toshimichi SAITO  

     
    INVITED PAPER

      Vol:
    E75-A No:3
      Page(s):
    294-298

    This article proposes a four dimensional autonomous hyperchaos generator whose nonlinear element is only one diode. The circuit is analyzed by regarding the diode as an ideal switch. Hence we can derive the two dimensional return map rigorously and its Lyapunov exponents confirm the hyperchaos generation. Also, a novel mathematical basis for the simplification to the ideal switch is given.

  • New Trend and Future Issues of Hardware Description Language and High-Level Synthesis

    Masaharu IMAI  

     
    INVITED PAPER

      Vol:
    E75-A No:3
      Page(s):
    307-313

    This paper discusses the trends and future issues in hardware description languages (HDL's) and high-level synthesis systems. First the importance of HDL's and high-level synthesis is described. Then, several HDL's and related CAD systems are briefly introduced. Finally, the requirements to future HDL's and highlevel synthesis systems are discussed from several points of view.

  • A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI

    Harufusa KONDOH  Seiji KOZAKI  Shinya MAKINO  Hiromi NOTANI  Fuminobu HIDANI  Masao NAKAYA  

     
    PAPER

      Vol:
    E75-C No:3
      Page(s):
    280-287

    A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.

  • A Layout System for Mixed A/D Standard Cell LSI's

    Ikuo HARADA  Hitoshi KITAZAWA  Takao KANEKO  

     
    PAPER

      Vol:
    E75-C No:3
      Page(s):
    322-332

    A layout system for mixed analog/digital standard cell LSI's is described. The system includes interactive floorplan and placement features and automatic global and channel router. In mixed analog/digital circuits, crosstalk noise causes chip performance degradation. Thus, the proposed global routing algorithm routes analog nets in areas that are free of digital nets as much as possible. The number of line crossovers, especially for analog nets, is minimized by both global and detailed routers, because these crossovers are the dominant factors in the crosstalk noise. Double width lines can be used to avoid unexpected voltage drops caused by parasitic resistances. A postprocess automatically puts up shield lines for very noise sensitive wirings to improve the S/N ratio. Experimental results show that the proposed algorithms are effective in reducing the number of crossovers and redundant vias.

  • Exploiting Separability in Numerical Analysis of Nonlinear Systems

    Kiyotaka YAMAMURA  

     
    INVITED PAPER

      Vol:
    E75-A No:3
      Page(s):
    285-293

    The aim of this article is to show the effectiveness of exploiting separability in numerical analysis of nonlinear systems. Separability is a valuable property of nonlinear mappings which appears with surprising frequency in science and engineering. By exploiting this property, computational complexity of many numerical algorithms can be substantially improved. However, this idea has not been received much attention in the fields of electronics, information and communication engineerings. In recent years, efficient algorithms that exploit the separability have been proposed in the areas of circuit analysis, homotopy methods, integer labeling methods, nonlinear programming, information theory, numerical differentiation, and neural networks. In this article, these algorithms are surveyed, and it is shown that considerable improvement of computational efficiency can be achieved by exploiting the separability.

  • Anechoic Chambers for EMI Test

    Yasutaka SHIMIZU  

     
    INVITED PAPER

      Vol:
    E75-B No:3
      Page(s):
    101-106

    Anechoic chambers have been effectively used for microwave propagation, electromagnetic interference (EMI) and immunity testing. The electromagnetic compatibility (EMC) problem has recently become serious and many of these chambers have been constructed. The results of a questionnaire survey sent to anechoic chamber manufacturers are described that a total of 450 anechoic chambers have been constructed in Japan since 1964. Twenty years ago the purpose of the chambers was microwave propagation research, but more than 50 each year have recently being built for EMC/EMI and immunity testing. Their size has gradually been reduced by the use of absorbing materials such as ferrite with dielectric materials. The lowest frequency of most chambers is 30MHz for the 3 m method of site attenuation.

  • Minimum-Width Method of Variable Ordering for Binary Decision Diagrams

    Shin-ichi MINATO  

     
    PAPER

      Vol:
    E75-A No:3
      Page(s):
    392-399

    Binary Decision Diagrams (BDDs) and Shared Binary Decision Diagrams (SBDDs), which are improved BDDs, are useful for implementing VLSI logic design systems. Recently, these representations, which are graph representations of Boolean functions, have become popular because of their efficiency in terms of time and space. The forms of the BDD vary with the order of the input variables though they represent the same function. The size of the graphs greatly depends on the order. The variable ordering algorithm is one of the most important issues in the application of BDDs. In this paper, we consider methods which reduce the graph size by reordering input variables on a given BDD with a certain variable order. We propose the Minimum-Width Method which gives a considerably good order in a practicable time and space. In the method, the order is determined by width of BDDs as a cost function. In addition, we show the effect of combining our method with the local search method, and also describe the improvement using the threshold. Experimental results show that our method can reduce the size of BDDs remarkably for most examples. The method needs no additional information, such as the topological information of the circuit. The results can be a measure for evaluation of other ordering methods.

  • Bifurcation Phenomena of a Distributed Parameter System with a Nonlinear Element Having Negative Resistance

    Hideo NAKANO  Hideaki OKAZAKI  

     
    PAPER

      Vol:
    E75-A No:3
      Page(s):
    339-346

    Dynamic behavior of a distributed parameter system described by the one-dimensional wave equation with a nonlinear boundary condition is examined in detail using a graphical method proposed by Witt on a digital computer. The bifurcation diagram, homoclinic orbit and one-dimensional map are obtained and examined. Results using an analog simulator are introduced and compared with that of the graphical method. The discrepancy between these results is considered, and from the comparison among the bifurcation diagrams obtained by the graphical method, it is denoted that the energy dissipation in the system considerably restrains the chaotic state in the bifurcation process.

  • Magnetic Radiations from Harness Wires of Spacecraft

    Minoru TSUTSUI  Hirotsugu KOJIMA  Isamu NAGANO  Hiroaki SATO  Toshimi OKADA  Hiroshi MATSUMOTO  Toshifumi MUKAI  Masayoshi KAWAGUCHI  

     
    PAPER

      Vol:
    E75-B No:3
      Page(s):
    174-182

    Radiation properties of magnetic noise from the harness wires of a spacecraft (GEOTAIL) have been studied experimentally and theoretically. A simulation experiment on the noise radiation using a minimum set of subsystems of the spacecraft has shown that the intensity and the directional patterns of the noise radiation from the wires were largely changed by the existence of a conductive plate near the harness wires. The change in the noise characteristics is explained by eddy currents induced in the conductive plate by the signal current flowing in the wires. The eddy currents distributed in the conductive plate were calculated by the Finite Element analysis Method (FEM). The magnetic flux densities calculated from both the source signal current and its induced eddy currents for the wiring configuration of the simulation experiment have shown to be consistent with the values obtained in the experiment. The results in the present study have provided us an important information on a wiring method to diminish noise radiation from harness wires.

  • GUNGEN: Groupware for New Idea Generation System

    Jun MUNEMORI  Yoji NAGASAWA  

     
    PAPER

      Vol:
    E75-A No:2
      Page(s):
    171-178

    The groupware for new idea generation system, GUNGEN, has been developed. GUNGEN consists of a distributed and cooperative KJ method support system and an intelligent productive work card support system. The system was implemented on a network consisting of a number of personal computers. The distributed and cooperative KJ method is carried out on computers. The ideas proposed by participants are classified into several groups on the basis of similarity and then a conclusion is derived. The intelligent productive work card support system can be used as a multimedia database to refer to the previous data of the distributed and cooperative KJ method.

  • High-Power Microwave Transmit-Receive Switch with Series and Shunt GaAs FETs

    Makoto MATSUNAGA  Kazuhiko NAKAHARA  

     
    PAPER-Microwave and Millimeter Wave Technology

      Vol:
    E75-C No:2
      Page(s):
    252-258

    A new monolithic transmit-receive GaAs FET switch has been developed, named the FET series-shunt connected TR switch and capable of switching high rf transmitting power. Both insertion loss and isolation limitations of this type TR switch have been analyzed using the switching cutoff frequency of the control FET, and the formula for calculating the rated power is provided. A unique feature of this switch is that the power handling of the switch is not limited by the FET gate break-down voltage but is limited by the saturation current, so higher handling power capability is available by using FETs with a larger gate periphery. A design example of the TR switch at a rated power of 8 W in the transmit mode as well as the results of an X band switch are presented.

  • Process Simulation for Laser Recrystallization

    Bo HU  Albert SEIDL  Gertraud NEUMAYER  Reinhold BUCHNER  Karl HABERGER  

     
    PAPER

      Vol:
    E75-C No:2
      Page(s):
    138-144

    Modeling and numerical simulation of crystal growth of Si film and heat transport in 3D structure were made for optimization of physical and geometrical parameters used during laser recrystallization. Based on simulations a new concept called micro-absorber was introduced for obtaining defect-free Si films.

  • Information Disseminating Schemes for Fault Tolerance in Hypercubes

    Svante CARLSSON  Yoshihide IGARASHI  Kumiko KANAI  Andrzej LINGAS  Kinya MIURA  Ola PETERSSON  

     
    PAPER-Graphs, Networks and Matroids

      Vol:
    E75-A No:2
      Page(s):
    255-260

    We present schemes for disseminating information in the n-dimensional hypercube with some faulty nodes/edges. If each processor can send a message to t neighbors at each round, and if the number of faulty nodes/edges is k(kn), then this scheme will broadcast information from any source to all destinations within any consecutive n+[(k+l)/t] rounds. We also discuss the case where the number of faulty nodes is not less than n.

  • An Efficient Method for Evaluating the Energy Distribution of Electrons in Semiconductors Based on Spherical Harmonics Expansion

    Davide VENTURA  Antonio GNUDI  Giorgo BACCARANI  

     
    PAPER

      Vol:
    E75-C No:2
      Page(s):
    194-199

    A spherical-harmonics expansion method is used to find approximate numerical solutions of the Boltzmann Transport Equation in the homogeneous case. Acoustic and optical phonon scattering, ionized impurity scattering as well as an energy band structure fitting the silicon density of states up to 2.6 eV above the conduction-band edge are used in the model. Comparisons with Monte Carlo data show excellent agreement, and prove that detailed information on the high-energy tail of the distribution function can be obtained at very low cost using this methodology.

  • Performance Limitation of Leaky Bucket Algorithm for Usage Parameter Control and Bandwidth Allocation Methods

    Naoaki YAMANAKA  Youichi SATO  Ken-ichi SATO  

     
    LETTER-Communication Networks and Service

      Vol:
    E75-B No:2
      Page(s):
    82-86

    One performance limitation of the "Leaky Bucket algorithm" for usage parameter control and traffic management in Asynchronous Transfer Mode (ATM) networks is analyzed. Simulation results show that the conventional statistical bandwidth allocation method, which uses the most bursty pattern permitted by the Leaky Bucket algorithm, can not guarantee the QOS of established Virtual Channels/Paths (VC/VP). As a result, the VC/VP bandwidth allocation method based on the Leaky Bucket algorithm is proven to be unsatisfactory.

  • Testing the k-Layer Routability in a Circular Channel--Case in which No Nets Have Two Terminals on the Same Circle--

    Noriya KOBAYASHI  Toshinobu KASHIWABARA  Sumio MASUDA  

     
    PAPER-Computer Aided Design (CAD)

      Vol:
    E75-A No:2
      Page(s):
    233-239

    Suppose that there are terminals on two concentric circles, Cin and Cout, with Cin inside of Cout. We are given a set of nets each of which consists of a terminal on Cin and a terminal on Cout. The routing area is the annular region between the two circles. In this paper, we present an O(nk-1) time algorithm for testing whether the given net set is k-layer routable without vias, where k2 and n is the number of nets.

  • Increase in Binaural Articulation Score by Simulated Localization Using Head-Related Transfer Function

    Shinji HAYASHI  

     
    PAPER

      Vol:
    E75-A No:2
      Page(s):
    149-154

    Binaural effects in two measures are studied. One measure is the detectable limen of click sounds under lateralization of diotic or dichotic noise signals, and the other is phoneme articulation score under localization or lateralization of speech and noise signals. The experiments use a headphones system with listener's own head related transfer function (HRTF) filters. The HRTF filter coefficients are calculated individually from the impulse responses due to the listener's HRTF measured in a slightly sound reflective booth. The frequency response of the headphone is compensated for using an inverse filter calculated from the response at the subject's own ear canal entrance point. Considering the speech frequency band in tele-communication systems is not sufficiently wide, the bandwidth of the HRTF filter is limited below 6.2 kHz. However, the experiments of the localization simulation in the horizontal plane show that the sound image is mostly perceived outside the head in the simulated direction. Under simulation of localization or lateralization of speech and noise signals, the phoneme articulation score increases when the simulation spatially separates the phonemes from the noise signals while the total signal to noise ratio for both ears is maintained constant. This result shows the binaural effect in speech intelligibility under the noise disturbance condition, which is regarded as a part of the cocktail party effect.

  • An Optimum Placement of Capacitors in the Layout of Switched Capacitor Networks

    Mineo KANEKO  Kimihiko KAZUI  Hiroaki KUNIEDA  

     
    PAPER-Analog Circuits and Signal Processing

      Vol:
    E75-A No:2
      Page(s):
    215-223

    An optimum placement of capacitors in the layout of Switched Capacitor networks is presented in this paper. The performance of integrated circuits is generally degraded by perturbations of physical parameters of each device and parasitic strays. The optimality imposed in this paper is the minimum degradation of a transfer function with respect to the distribution of capacitance values. A capacitance value per unit area fabricated on a LSI chip is assumed to be perturbed linearly with its x and y coordinates. The capacitor placement is determined so that the effects of such perturbation of capacitances to the overall transfer-characteristics are canceled. As the result, input-output transfer function will stay nominal under the linear perturbation model with arbitrary gradients.

22621-22640hit(22683hit)