This paper demonstrates a polyimide/alumina-ceramic multilayer MIC analog phase shifter with a large phase shift. First, a novel active inductor, similar to the previously reported active inductor but with a shunt variable resistor inserted in the feedback loop, is proposed for miniaturizing the circuit. The chip size of the fabricated GaAs MESFET active inductor is less than 0. 52 mm2. Next, a low-loss analog phase shifter with a large phase shift is presented. This is constructed in an MIC structure with the active inductors, the varactor diodes and the low-loss polyimide/alumina-ceramic multilayer broad-side coupler. Furthermore, since the amount of the phase shift is the sum of the two individual tuning ranges attributed to the active inductors and varactor diodes, a large phase shift is obtained compared to the case where only the varactor diodes are tunable. Thus, a phase shift of more than 270 within 2-dB insertion loss from 2. 1 to 2. 4 GHz is obtained with the fabricated single-stage reflection-type analog phase shifter. The total power consumption is less than 80 mW.

In this paper, we consider the selection of analysis filters used in the delayless subband adaptive digital filter (SBADF) and propose to use simple analysis filters to reduce the computational complexity. The coefficients of filters are determined using the components of the first order Hadamard matrix. Because coefficients of Hadamard matrix are either 1 or -1, we can analyze signals without multiplication. Moreover, the conditions for convergence of the proposed method is considered. It is shown by computer simulations that the proposed method can converge to the Wiener filter.

This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals. The encoder consists of four major building functions which are color space converter, digital filters, color modulator, and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance SNR of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs are luminance (Y), chrominance (C), and composite video baseband (Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Verilog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 36 k gates and is implemented by using 0. 65 µm CMOS process.

This paper presents two kinds of simplification methods for incompletely specified sequential machines. The strategy of the methods is that as many states in original machines are covered in the simplification processes as possible. The purpose of the methods is to derive a simplified machine having either the largest maximal compatible set or its subset. With the methods, one of the minimal machines can not be always derived, but a near-minimal machine can be obtained more quickly with less memory, since they need not derive all the compatible sets. In this paper, the effectiveness of the methods is checked by applying them to simplification problems of incompletely specified machines generated by using random numbers, and of the MCNC benchmark machines. The experimental results show that our methods can derive a simplified machine quickly, especially for machines having a great number of states or don't care rate.

We present experimental results for a structural learning method of feed-forward neural-network classifiers using Principal Component Analysis (PCA) network and Species Genetic Algorithm (SGA). PCA network is used as a means for reducing the number of input units. SGA, a modified GA, is employed for selecting the proper number of hidden units and optimizing the connection links. Experimental results show that the proposed method is a useful tool for choosing an appropriate architecture for high dimensions.

In this paper, a new architecture of Multilayer Neural Network (MNN) with on-chip learning for effective hardware implementation is proposed. To reduce the circuit size, threshold function is used as neuron's activating function and simplified back-propagation algorithm is employed to provide on-chip learning capability. The derivative of the activating function is modified to improve the rate of successful learning. The learning performance of the proposed architecture is tested by system-level simulations. Simulation results show that the modified derivative function improves the rate of successful learning and that the proposed MNN has a good generalization capability. Furthermore, the proposed architecture is implemented on field programmable gate array (FPGA). Logic-level simulation and preliminary experiment are conducted to test the on-chip learning mechanism.

This paper describes a neuro-based optimization algorithm for three dimensional (3-D) rectangular puzzles which are the problems to arrange the irregular-shaped blocks so that they perfectly fit into a fixed three dimensional rectangular shape. First, the fitting function of the 3-D block, which means the fitting degree of each irregular block to the neighboring block and the rectangular configuration, is described. Next, the energy function for the 3-D rectangular puzzles is proposed, where the horizontal rotation of the block is also considered. Finally, our optimization method is applied to several examples using the 3-D analog neural array and it is shown that our algorithm is useful for solving 3-D rectangular puzzles.

This paper describes a theoretical foundation of fuzzy morphological operations and architectural extension of the shared-weight neural network (SWNN). The network performs shift-invariant filtering using fuzzy-morphological operations for feature extraction. The nodes in the feature extraction stage employ the generalized-mean operator to implement fuzzy-morphological operations. The parameters of the SWNN, weights, morphological structuring element and fuzziness, are optimized by the error back-propagation (EBP) training method. The parameter values of the trained SWNN are then implanted into the extended SWNN (ESWNN) which is a simple convolution neural network. The ESWNN architecture dramatically reduces the amount of computation by avoiding segmentation process. The neural network is applied to automatic recognition of a vehicle in visible images. The network is tested with several sequences of images that include targets ranging from no occlusion to almost full occlusion. The results demonstrate an ability to detect occluded targets, while trained with non-occluded ones. In comparison, the proposed network was superior to the Minimum-Average Correlation filter systems and produced better results than the ordinary SWNN.

In this paper, a new traffic sign detection algorithm and a symbol recognition algorithm are proposed. For a traffic sign detection, a dominant color transform is introduced, which serves as a tool of highlighting a dominant primary color, while discarding the other two primary colors. For a symbol recognition, the curvilinear shape distribution on a circle centered on the centroid of the symbol, called a circular pattern vector, is used as a spatial feature of the symbol. The circular pattern vector is invariant to scaling, translation, and rotation. As simulation results, the effectiveness of traffic sign detection and recognition algorithms are confirmed.

This paper proposes an automatic structural programming system. Genetic Programming achieves success for automatic programming using the evolutionary process. However, the approach doesn't deal with the essential program concept in the sense of what is called a program in software science. It is useful that a program be structured by various sub-structures, i. e. subroutines, however, the above-mentioned approach treats a single program as one sequence. As a result of the above problem, there is a lack of reusability, flexibility, and a decreases in the possibility of use as a utilitarian programming system. In order to realize a structural programming system, this paper proposes a method which can generate a program constructed by subroutines, named formula, using the evolutionary process.

This paper proves a general sampling theorem, which is an extension of Shannon's classical theorem. Let o be a closed subspace of square integrable functions and call o a signal space. The main aim of this paper is giving a necessary and sufficient condition for unique existence of the sampling basis {Sn}o without band-limited assumption. Using the general sampling theorem we rigorously discuss a frequency domain treatment and a general signal space spanned by translations of a single function. Many known sampling theorems in signal spaces, which have applications for multiresolution analysis in wavelets theory are corollaries of the general sampling theorem.

The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.

We propose a Generalized Order Statistic Cell Averaging (GOSCA) CFAR detector. The weighted sums of the order statistics in the leading and lagging reference windows are utilized for the background level estimate. The estimate is obtained by averaging the weighted sums. By changing the weighting values, various CFAR detectors are obtained. The main advantage of the proposed GOSCA CFAR detector over the GOS CFAR detector is to reduce a computational time which is critical factor for the real time operation. We also derive unified formulas of the GOSCA CFAR detector under the noncoherent integration scheme. For Swerling target cases, performances of various CFAR detectors implemented using the GOSCA CFAR detector are derived and compared in homogeneous environment, and in the case of multiple targets and clutter edges situations.

In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.

This paper proposes a fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis of digital signal processing hardwares. The objective of the algorithm is to minimize the costs for functional units and registers and to maximize connectivity under given computation time and initiation interval. Incorporating the connectivity in a scheduling stage can reduce multiplexer counts in resource binding. The algorithm maximizes connectivity with maintaining low time complexity and obtains datapath designs with totally small hardware costs in the high-level synthesis environment. The algorithm also resolves inter-iteration data dependencies and thus realizes pipelined datapaths. The experimental results demonstrate that the proposed algorithm reduces the multiplexer counts after resource binding with maintaining low costs for functional units and registers compared with eight conventional schedulers.

This paper presents a new architecture for multiple-input signature analyzers. The proposed signature analyzer with Hδ inputs is designed by parallelizing a GLFSR(δ,m), where δ is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by Pradhan and Gupta, is a general framework for representing LFSR-based signature analyzers. The parallelization technique described in this paper can be applied to any kind of GLFSR signature analyzer, e. g. , SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with Hδ inputs requires less complex hardware than either single GLFSR(Hδ,m)s or a parallel construction of the H original GLFSR(δ,m)s. It is also shown that the proposed signature analyzer, while requiring simpler hardware, has comparable aliasing probability with analyzers using conventional GLFSRs for some CUT error models of the same test response length and test time. The proposed technique would be practical for testing CUTs with a large number of output sequences, since the test circuit occupies a smaller area on the LSI chip than the conventional multiple-input signature analyzers of comparable aliasing probability.

This paper presents a technique to transmit 16QAM signals in mobile radio environments by using extended symbol-aided estimation (ESAE) method for compensating the multipath fading effect. The main results of this paper are the symbol error rate (SER) performance analyses for BPSK and 16QAM systems using the proposed estimation method under Rician fading. The analytical results demonstrate better performance of the proposed systems compared with those of the conventional systems under fast and severe fading, especially in the region of high signal to noise ratio.

A function approximation scheme for image restoration is presented to resolve conflicting demands for smoothing within each object and differentiation between objects. Images are defined by probability distributions in the augmented functional space composed of image values and image planes. According to the fuzzy Hough transform, the probability distribution is assumed to take a robust form and its local maxima are extracted to yield restored images. This statistical scheme is implemented by a feedforward neural network composed of radial basis function neurons and a local winner-takes-all subnetwork.

We study the pm-degrees and pT-degrees of immune and bi-immune sets. We demonstrate the existence of incomparable pT-immune degrees in deterministic time classes.

This paper aims at developing forward link power control methods for CDMA cellular systems. The purpose is to allocate available power to as many mobiles as possible. When a power allocation in the network is fixed, the power assigned to the cell where rare mobiles communicate is wasting, and moreover, is prohibitive if other cells fall short of transmitting power. In this case, re-allocation is necessary. Power control in this paper takes the form of allocating pilot and traffic power according to the different needs from each cell. Especially, the pilot power control method tends to balance nonuniformly imposed load through the network, and hence helps the network resources be utilized equally. With the proposed pilot control method, the number of simultaneously communicating mobiles increases by 10-25% over the reference methods.