We have developed a low bit-rate video coding using a video digital signal processor (DSP) called VDSP1χ, which performs real-time encoding and decoding for discrete cosine transform-(DCT-) based algorithms, such as ITU-T H. 261, H. 263 and wavelet-based subband encoding algorithms. This LSI features a processing unit which implements wavelet filters at high speeds, a compact DCT circuit, and a fast, flexible DRAM interface for low-cost systems. This system is capable of processing quarter common intermediate format (QCIF)(176144 pixels) size pictures at a rate greater than 15 frames/s.

In live multimedia applications with multiple videos, it is necessary to develop an efficient mechanism of multiplexing several MPEG video streams into a single stream and transmitting it over network without wasting excessive bandwidth. In this paper, we present an efficient multiplexing and traffic smoothing scheme for multiple variable bit rate (VBR) MPEG video streams in live video applications with finite buffer sizes. First, we describe the constraints imposed by the allowable delay bound for each elementary stream and by the multiplexer/receiver buffer sizes. Based on these constraints, a new multiplexing and traffic smoothing scheme is designed in such a way as to smooth maximally the multiplexed transmission rate by exploiting temporal and spatial averaging effects, while avoiding the buffer overflow and underflow. Through computer experiments based on an MPEG-coded video trace of Star-wars, it is shown that the proposed scheme significantly reduces the peak rate, coefficient of variation, and effective bandwidth of the multiplexed transmission rate.

Topological Walk is an algorithm that can sweep an arrangement of n lines in O(n2) time and O(n) space. This paper revisits Topological Walk to give its new interpretation in contrast with Topological Sweep. We also survey applications of Topological Walk to make the distinction clearer.

We consider linearizable implementations of shared FIFO queues and general deterministic objects on a distributed message-passing system which provides a real-time timer. The efficiency of an implementation is measured by the worst-case response time res_time(op) for each operation op of the implemented objects. We show the following results under the assumption that all message delays are in the range [d-u,d] for some constants d and u (0 u d). We first present an implementation of deterministic objects with res_time(opa)=u for any ack-type operation opa and res_time(opv)=2d for any val-type operation opv, where an ack-type operation is an operation which always returns a unique response and a val-type operation is an operation which is not ack-type. We also consider an implementation of FIFO queues, which have two kinds of operations, enq(v) and deq. We show that, for any implementation of FIFO queues, (1) res_time(enq(v)) u(n-1)/n holds for some v where n is the number of processes, and (2) res_time(deq) d+u/2 holds in the case of u (2/3)d.

A floorplan is a partition of a rectangle into subrectangles, each of which is associated with a module. Zero-wasted-area layouts are known to exist when the height and width of modules are constrained only by the area, and several methods have been proposed for deriving such layouts. However, because these methods are global and indirect, they are inherently slow. We propose a new algorithm which simulates the air-pressure mechanics. It begins with a layout, which is not necessarily feasible, and iterates the movement of one wall at a time to the force-balancing position. The key issue is that it is guaranteed that every movement makes a current layout approach a zero-wasted-area layout by the measure of energy which is defined here. Experimental results on the example in several literatures and artificially made complex examples showed very fast convergence. The algorithm is evolved to methods which move all the walls simultaneously, resulting in a further speed enhancement.

As a super class of tournament digraphs, Bang-Jensen, Huang and Prisner defined an in-tournament digraph (in-tournament for short) and investigated a number of its nice properties. The in-tournament is a directed graph in which the set of in-neighbors of every vertex induces a tournament digraph. In other words, the presence of arcs (x,z) and (y,z) implies that exactly one of (x,y) or (y,x) exists. In this paper, we propose, for in-tournaments, parallel algorithms for examining the existence of a Hamiltonian path and a Hamiltonian cycle and for constructing them, if they exist.

In communication networks there is a growing need for ensuring that networks maintain service despite failures. To meet the need, the concept of δ-reliable channel is introduced; it is a set of communication channels along a set of paths. The δ-reliable channel meets the requirement that if a link or node fails, failure is limited to a maximum of δ f (f total capacity of the channels, and 0<δ 1). The max-flow min-cut theorem of δ-reliable flow has been proved for the single-commodity case. In this paper we give a method for evaluating the maximum δ-reliable flow between a specified pair of vertices for single commodity case. The method consists of a maximum of 1/δ iterations of calculations of the maximum flow value.

For a given N-vertex graph H, a graph G obtained from H by adding t vertices and some edges is called a t-FT (t-fault-tolerant) graph for H if even after deleting any t vertices from G, the remaining graph contains H as a subgraph. For the n-dimensional cube Q(n) with N vertices, a t-FT graph with an optimal number O(tN+t2) of added edges and maximum degree of O(N+t), and a t-FT graph with O(tNlog N) added edges and maximum degree of O(tlog N) have been known. In this paper, we introduce some t-FT graphs for Q(n) with an optimal number O(tN+t2) of added edges and small maximum degree. In particular, we show a t-FT graph for Q(n) with 2ctN+ct2((logN)/C)C added edges and maximum degree of O(N/(logC/2N))+4ct.

Let H=(V(H),E(H)) be a directed graph with distinguished vertices s and t. An st-path in H is a simple directed path starting from s and ending at t. Let (H) be defined as { SS is the set of vertices on an st-path in H (s and t are excluded)}. For an undirected graph G=(V(G),E(G)) with V(G) V(H)- { s,t }, if the family of maximal independent sets of G coincides with (H), we call H an MIS-diagram for G. In this paper, we provide a necessary and sufficient condition for a directed graph to be an MIS-diagram for an undirected graph. We also show that an undirected graph G has an MIS-diagram iff G is a cocomparability graph. Based on the proof of the latter result, we can construct an efficient algorithm for generating all maximal independent sets of a cocomparability graph.

To further increase the capacity of the DS-CDMA reverse-link, this paper investigates the effectiveness of interference rejection weight control (IRWC) for the pilot symbol-assisted coherent multistage interference canceller (PSA-COMSIC) using recursive channel estimation (RCE). First, a bit error rate (BER) expression of the serial (successive) and parallel type hard decision multistage interference canceller (MSIC) with IRWC using Gaussian approximation for multiple access interference (MAI) are presented for no fading channels. It is theoretically shown that IRWC is effective in mitigating the interference replica generation error in hard decision MSIC. Next, the BER performance of PSA-COMSIC using IRWC in a multipath Rayleigh fading channel when channel coding is applied is evaluated by computer simulations. The BER performance and capacity are evaluated not only for the conventional serial and parallel types but also for serial/parallel (S/P) hybrid type and non-linear/linear (N/L) hybrid type schemes, both of which are effective in significantly reducing the demodulation processing delay. The simulation results demonstrate that, in interference-limited channels where the back ground noise is negligible, the capacity of serial type PSA-COMSIC using IRWC is about 10% higher than that without IRWC. It is also found that if we can accept a slight capacity degradation compared to the serial type PSA-COMSIC, S/P hybrid schemes are effective in reducing the demodulation processing delay.

The packing problem is to pack given items into given containers as efficiently as possible under various constraints. It is fundamental and significant with variations and applications. The Set-Bin-Packing (SBP) is a class of packing problems: Pack given items into as few bins which have the same capacity where every item is a set and a bin can contain items as long as the number of distinct elements in the union of the items equals to or less than the capacity. One of applications is in FPGA technology mapping, which is our initial motivation. In this paper, the computational complexity of SBP is studied with respect to three parameters α, γ, and δ which are the capacity, the upper bound of the number of elements in an item, and the upper bound of the number of items having an element, respectively. In contrast that the well known Integer-Bin-Packing (IBP) is NP-hard but is proved that even a simplest heuristics First-Fit-Decreasing (FFD) outputs exact solutions as long as α 6, our result reveals that SBP remains NP-hard for a small values of these parameters. The results are summarized on a 3D map of computational complexities with respect to these three parameters.

An approximation algorithm composed of a digital neural network (DNN) and a modified greedy algorithm (MGA) is presented for the board-level routing problem (BLRP) in a logic emulation system based on field-programmable gate arrays (FPGA's) in this paper. For a rapid prototyping of large scale digital systems, multiple FPGA's provide an efficient logic emulation system, where signals or nets between design partitions embedded on different FPGA's are connected through crossbars. The goal of BLRP, known to be NP-complete in general, is to find a net assignment to crossbars subject to the constraint that all the terminals of any net must be connected through a single crossbar while the number of I/O pins designated for each crossbar m is limited in an FPGA. In the proposed combination algorithm, DNN is applied for m = 1 and MGA is for m 2 in order to achieve the high solution quality. The DNN for the N-net-M-crossbar BLRP consists of N M digital neurons of binary outputs and range-limited non-negative integer inputs with integer parameters. The MGA is modified from the algorithm by Lin et al. The performance is verified through massive simulations, where our algorithm drastically improves the routing capability over the latest greedy algorithms.

Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. The target FPGA architecture is developed for transport processing. In order to implement more various circuits flexibly, it has three-input lookup tables (LUTs) as minimum logic cells. Since its logic granularity is finer than that of conventional FPGAs, it requires more routing resources to connect them and minimization of routing congestion is indispensable. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, in Step 1 an added LUT is placed with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then in Step 2 preplaced LUTs are moved to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate that, if the number of added LUTs is at most 20% of the number of initial LUTs, our algorithm generates the reconfigured layouts whose routing congestion is as small as that obtained by executing a conventional placement and global routing algorithm. Run time of our algorithm is within approximately one second.

We have proposed a non-invasive method for diagnosis of the early stage of atherosclerosis, namely, the detection of small vibrations on the aortic wall near the heart by using ultrasound diagnostic equipment. It is, however, necessary to confirm the effectiveness of such measurement of the pulse wave velocity for quantitative evaluation of the local characteristics of atherosclerosis. It is well known that Young's modulus of a tube wall, estimated from measured pulse wave velocity, depends on inner pressure because of the non-linear relationship between the inner pressure and the change of volume in the tube. The inner pressure, however, changes during the period of one heartbeat. In this experimental study, we found for the first time that Young's modulus of the tube wall, estimated from the measured pulse wave velocity, depends not only on the diastolic pressure but also on the pulse pressure and the pressure gradient of the systolic period.

This paper proposes a new design method of a nonlinear filtering algorithm in continuous-time stochastic systems. The observed value consists of nonlinearly modulated signal and additive white Gaussian observation noise. The filtering algorithm is designed based on the same idea as the extended Kalman filter is obtained from the recursive least-squares Kalman filter in linear continuous-time stochastic systems. The proposed filter necessitates the information of the autocovariance function of the signal, the variance of the observation noise, the nonlinear observation function and its differentiated one with respect to the signal. The proposed filter is compared in estimation accuracy with the MAP filter both theoretically and numerically.

Multi-recast techniques make it possible for a voter to participate in a sequence of different designated votings by using only one ticket. In a multi-recastable ticket scheme for electronic voting, every voter of a group can obtain an m-castable ticket (m-ticket), and through the m-ticket, the voter can participate in a sequence of m different designated votings held in this group. The m-ticket contains all possible intentions of the voter in the sequence of votings, and in each of the m votings, a voter casts his vote by just making appropriate modifications to his m-ticket. The authority cannot produce both the opposite version of a vote cast by a voter in one voting and the succeeding uncast votes of the voter. Only one round of registration action is required for a voter to request an m-ticket from the authority. Moreover, the size of such an m-ticket is not larger than that of an ordinary vote. It turns out that the proposed scheme greatly reduces the network traffic between the voters and the authority during the registration stages in a sequence of different votings, for example, the proposed method reduces the communication traffic by almost 80% for a sequence of 5 votings and by nearly 90% for a sequence of 10 votings.

The asymptotic behavior of the recurrence time with fidelity criterion is discussed. Let X= be a source and Y= a database. For a Δ>0 and an integer l>0 define (Y,X,Δ) as the minimum integer N satisfying dl(,) Δ subject to a fidelity criterion dl. In this paper the following two i. i. d. cases are considered: (A) Xi P and Yi Q, where P and Q are probability distributions on a finite alphabet, and (B) Xi N(0,1) and Yi N(0,1). In case (A) it is proved that (1/l)log2(Y,X,Δ) almost surely converges to a certain constant determined by P, Q and Δ as l. The Kac's lemma plays an important role in the proof on the convergence. In case (B) it is shown that there is a quantity related to (1/l)log2 (Y,X,Δ) that converges to the rate-distortion bound in almost sure sense.

This letter describes new active building blocks defined as the generalized voltage conveyor (GVC) and the generalized current conveyor (GCC). A very simple practical realization of the GVC using the second generation current conveyors (CCII) is given. The special cases of the first generation voltage conveyor (VCI) and the second generation voltage conveyor (VCII) are also considered. A practical realization of the GCC using the CCII is also given. Applications of the voltage and current conveyors in oscillators are considered.

The features for the integration of 1Tr/1C DRAM and logic for graphic and multimedia applications are surveyed. The key circuit/process technology for large scale embedded DRAM cores is described. The methods to improve transistor performance and gate density are shown. Noise immunity design and easy customization techniques are also introduced.

We present techniques to implement fair-sharing on both link bandwidth and buffer space in a switch or router. Together they possess the following merits: 1. solving the counter-overflow problem; 2. avoiding the "credit" accumulation issue; 3. integrating bandwidth allocation with buffer management. The simplicity of this method makes it a viable candidate for implementational use on switches and routers.