The adaptive associative memory proposed by Ma is used to construct a new model of semantic network, referred to as associative semantic memory (ASM). The main novelty is its computational effectiveness which is an important issue in knowledge representation; the ASM can do inference based on large conceptual hierarchies extremely fast-in time that does not increase with the size of conceptual hierarchies. This performance cannot be realized by any existing systems. In addition, ASM has a simple and easily understandable architecture and is flexible in the sense that modifying knowledge can easily be done using one-shot relearning and the generalization of knowledge is a basic system property. Theoretical analyses are given in general case to guarantee that ASM can flawlessly infer via pattern segmentation and recovery which are the two basic functions that the adaptive associative memory has.

This paper proposes a novel representation scheme for self-healing networks, and estimates the performance of restoration algorithms in terms of survivability. This representation is based on that of ring networks. For an arbitrary topology, the network is partitioned into ring sub-networks which are independent of each other, and we consider an extended network constructed by the concatenation of the ring sub-networks. After the statement of the general case, examples of a self-healing ring and a Digital Cross-connect System(DCS)based network are described.

For Cable-To-The-Air network providing a seamless access network in both indoor and outdoor, direct optical switching CDMA scheme is newly proposed to multiplex any types of radio signals. In two types of connection methods, optical switch connection and optical coupler connection systems, the received carrier-to-interference-plus-noise power ratios are theoretically analyzed. It is clarified that in the optical switch connection connection system, by introducing the additional optical gain at each radio base station, the carrier-to-interference-plus-noise power ratios for all radio base stations and the connected number of radio base stations can be improved compared with the OC connection system.

This paper describes the recently developed 816 delivery and coupling switch (DC-switch) boards for constructing a 320-Gb/s throughput (2. 5 Gb/s 8 multiplexed wavelengths 16 incoming/outgoing link pairs) optical path cross-connect (OPXC) system based on wavelength path (WP) and virtual wavelength path (VWP) schemes. The DC-switch-based OPXC system, compared with conventional space division switch (SD-switch)-based OPXC system architecture, is shown to be superior in terms of; i) high link modularity, ii) upgradability from WP network to VWP network, iii) better transmission characteristics, and iv) lower total switching power consumption. Therefore, the DC-switch-based OPXC system can realize cost-effective optical path networks. The developed DC-switches exploit the silica-based planar lightwave circuit (PLC) technologies, and DC-switch board size is 300330 mm2 (one switch). The worst values of the insertion loss of the board, ON/OFF ratio, and polarization dependent loss are 14. 5 dB, 34 dB and 0. 5 dB, respectively. Moreover, even though switching is realized by thermo-optic effects, the optical output level varies by only 0. 7 dB and 0. 8 dB for ON- and OFF-state signals, respectively, when the environmental temperature is varied from 5 to 65 .

A GaAs power amplifier IC has been developed for 1. 9-GHz digital mobile communication applications, such as the handsets of the Japanese personal handy phone system (PHS), which was assembled into a very small 0. 012-cc surface mount plastic package. This power amplifier using refractory WNx/W self-aligned gate MESFETs with p-pocket layers can operate with high efficiency and low distortion with a single 3-V supply. A very low dissipated current of 119 mA was obtained with an output power of 21. 1 dBm and a low 600-kHz adjacent channel leakage power (ACP) of -63 dBc for π/4-shifted quadrature phase shift keying (QPSK) modulated input.

Huynen has already provided a method to decompose a Mueller matrix in order to retrieve detailed target information in a polarimetric radar system. However, this decomposition sometimes fails in the presence of small error or noise in the elements of a Mueller matrix. This paper attempts to improve Huynen's decomposition method. First, we give the definition of stable decomposition and present an example, showing a problem of Huynen's approach. Then two methods are proposed to carry out stable decompositions, based on the nonlinear least square method and the Newton's method. Stability means the decomposition is not sensitive to noise. The proposed methods overcomes the problems on the unstable decomposition of Mueller matrix, and provides correct information of a target.

Parallel Transaction Processing (TP) systems have great potential to serve the ever-increasing demands for high transaction processing rate. This potential, however, may not be reached due to the data contention and the widely-used two-phase locking (2PL) Concurrency Control (CC) method. In this paper, a distributed locking-based CC policy called LWDC (Local Wait-Depth Control) was proposed for dealing with this problem for the shared-nothing parallel TP system. On the basis of the LWDC policy, an algorithm called LWDCk was designed. Using simulation LWDCk was compared with the 2PL and the base-line Distributed Wait-Depth Limited (DWDL) CC methods. Simulation studies show that the new algorithm offers better system performance than those compared.

In land mobile communication, CMA (Constant Modulus Algorithm) has been studied to reduce multipath fading effect. By this method, the transmitted power is not used efficiently since all the multipath components have the same information. To make use of received power efficiently, we propose a Blind Multiple Beam Adaptive Array. It has the following three feature points. First, we use CMA which can reduce the multipath fading effect to some extent without training signal. Second, LMS algorithm which can capture the multipath components which are separated from the reference signal by some extent. Third, we use FDF (Fractional Delay Filter) and TED (Timing Error Detector) loop which can detect and compensate fractional delay. As a result of utilizing the multipath components which is suppressed by CMA, the proposed technique achieves better performance than CMA adaptive array.

Field experiments using the 2 GHz carrier frequency band were conducted nearby Tokyo to evaluate the effect of joint use of Rake combining and antenna diversity and also the effect of spreading chip rate (or bandwidth) on the achievable bit error rate (BER) performance and the mobile station transmit power distribution of power controlled coherent DS-CDMA reverse-link (mobile-to-base). Four chip rates, 0. 96, 1. 92, 3. 84, and 7. 68 Mcps, were used. The command interval and power step size of the fast transmission power control (TPC) used in the experiments, 1. 25 ms and 1 dB, respectively, were based on measurements of signal-to-interference plus background noise power ratio (SIR) after Rake combining. The field experiments demonstrate that the joint use of antenna diversity and Rake combining significantly improves the BER performance and, furthermore, that increasing the chip rate improves the BER performance and decreases the transmit power because of enhanced Rake combining through an increase in the number of resolved paths.

In this paper, we apply the Semi-markov Memory and Cache coherence Interference (SMCI) model, which we had proposed for invalidating based cache coherent parallel computers, to an updating based protocol. The model proposed here, the SMCI/Dragon model, can predict performance of cache coherent parallel computers with the Dragon protocol as well as the original SMCI model for the Synapse protocol. Conventional analytic models by stochastic processes to describe parallel computers have the problem of numerical explosion in the number of states necessary as the system size increases. We have already shown that the SMCI model achieved both the small number of states to describe parallel computers with the Synapse protocol and the inexpensive computation cost to predict their performance. In this paper, we demonstrate generality of the SMCI model by applying it to the another cache coherence protocol, Dragon, which has opposite characteristics than Synapse. We show the number of states required by constructing the SMCI/Dragon model is only 21 which is as small as SMCI/Synapse, and the computation cost is also the order of microseconds. Using the SMCI/Dragon model, we investigate several comparative experiments with widely known simulation results. We found that there is only a 5. 4% differences between the simulation and the SMCI/Dragon model.

A simulation methodology to analyze hot-carrier degradation due to bidirectional stressing in a static RAM circuit has been developed. The bidirectional stressing of pass transistors can approximate to unidirectional stressing. The effective stress direction of each NMOSFET can be determined by the higher of the two junction voltages at the peak substrate current generation. Aged SPICE parameter sets extracted in the forward or in the reverse mode are selected for simulating the degradation of each NMOSFET. Furthermore, effects of each NMOSFET degradation on the degraded circuit behavior are simulated. This technique helps detect an NMOSFET having the largest influence on the circuit aging, improving circuit reliability. The methodology was successfully applied to an SRAM device, and was validated by low temperature bias test data.

The purpose of this letter is to investigate the stability conditions of the active two port networks having some restrictions on load and source terminations, and then they have been obtained. Next, these results and the previous stability coditions are investigated, and then the new combined stability condition are proposed.

It is important to know phase offsets of a binary code in the field of mobile communications because different phase offsets of the same code are used to distinguish signals received at a mobile station from those of different base stations. When the period of the code is not very long, the relative phase offset between the code and its shifted code can be found by counting the number of bits delayed from the code of the same bit streams. But as the period of the code increases, it becomes difficult to find the phase offset. This paper proposes a new method to calculate the phase offset of a binary code. We define an accumulator function, which is used to calculate the phase offsets between the code and its shifted code. Also the properties of the accumulator function are investigated. This number theoretical approach and its results show that this method is very easy for the phase offset calculation. Its application to the code division multiple access (CDMA) system to define a reference code is given. The simple circuit realization of the accumulator function to calculate the phase offset between the received code and receiver stored replica code is described.

The visual secret sharing scheme (VSSS) proposed by Naor and Shamir provides a way to encrypt a secret black-white image into shares and decrypt the shares without using any cryptographic computation. This paper proposes an extension of VSSS to sharing of color or gray-scale images. In this paper (k,n) VSSS for images with J different colors is defined as a collection of J disjoint subsets in n-th product of a finite lattice. The subsets can be sequentially constructed as a solution of a certain simultaneous linear equation. In particular, the subsets are simply expressed in (n,n), (n-1,n) and (2,n) cases. Any collections of k-1 shares reveal no information on a secret image while stacking of k arbitrary shares reproduces the secret image.

The authors propose a novel waveguide two-way power divider, named as τ-junction, in a feed waveguide of a single-layer slotted waveguide array antenna. This junction occupies only a small space and is placed in the middle of a cascade of several power dividers. It suppresses the long line effect and widens the bandwidth of the feed waveguide. The junction has two inductive walls; one is for suppressing the reflection and the other is for controlling the ratio of divided power to the two output ports. Analysis using Galerkin's method of moments is verified by experiments of a 4 GHz-band model. We install the junctions in a 12 GHz-band single-layer slotted waveguide array. The gain reduction at the band-edge is suppressed.

Media processors have emerged so that a single LSI can realize multiple multimedia functions, such as graphics, video, audio and telecommunication with effectively shared hardware and flexible software. First, the difference between media processors and general-purpose microprocessors with multimedia extensions is clarified. Features for processes and data in the multimedia applications are summarized and are followed by the multimedia enhancements that the recent general-purpose microprocessors use. The architecture for media processors reflects the further optimized utilization of these features and realizes better price-performance ratio than the general-purpose microprocessors. Finally, the future directions of media processors are estimated, based on the performance, the power dissipation and the die size of the present microprocessors with multimedia extensions and the present media processors. The demand to improve the price-performance ratio for the whole system and to reduce the power consumption makes the media processor evolve into a system processor, which integrates not only the media processor but also the function of a general-purpose microprocessor, various interfaces and DRAMs.

Quality of service requirements are satisfied conjointly by the service model, which determines how resources are shared and by network engineering, which determines how much capacity is provided. In this paper we consider the impact of the adopted charging scheme on the feasibility of fulfilling QoS requirements. We identify three categories of charging scheme based respectively on flat rate pricing, congestion pricing and transaction pricing.

Physics principles of a new type of microwave input amplifiers are described. Cyclotron wave electrostatic amplifier (CWESA) has a low noise level, broad band, switchable gain, super high self-protection against microwave overloads, rapid recovery and small DC consumption. CWESAs are widely used in Russian pulse Doppler radars and other systems.

We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.

Cell delay variation (CDV) has been considered as an important performance measure due to the stringent timing requirement for video and multimedia services. In this paper we address the problem of CDV performance guarantee in virtual path (VP)-based ATM multiplexing. We propose a rate-based and non-work-conserving scheduling algorithm, called interleaved round robin (IRR), for serving traffic streams among VPs into the outgoing link. Through our performance analysis, the proposed scheme is capable of providing upper and lower bounds on the inter-visit time (IVT) for each VP, where the difference between the upper bound and the lower bound is simply dependent upon the number of multiplexed VPs. The distribution of VP IVT scheduled by an IRR server can also be well approximated using a random incidence technique. In addition to the VP-level CDV performance, we further examine the virtual connection (VC)-level CDV incurred within a multi-stage network through simulation study. The simulation results show that the IRR server can provide traffic regulation and smoothness at each network node. Moreover, the CDV distribution of a tagged VC is insensitive to the source traffic characteristic, node location, and the hop count traversed in the network.