In this paper, we investigate a low-power architecture for designs modeled as an Extended Finite State Machine (EFSM). It is based on the general dynamic power management concept, in which the redundant computation can be dynamically disabled to reduce the overall power dissipation. The contribution of this paper is mainly a systematic procedure to identify almost maximal amount of redundant computation in a design given as an EFSM. There are two levels of redundant computation to be exploited--one is based on the machine state information, while the other is based on the transition information. After the extraction of the redundant computation, a low-power architecture using input gating is proposed to synthesize the final circuit. We tested the technique on a design computing a number's modulo inverse. Experimental results show that 31% power reduction can be achieved at the costs of 2% timing penalty and 16% area overhead.

This paper presents the definition and implementation design of a low power data bus encoding scheme dedicated to system on chip video architectures. Trends in CMOS technologies focus the attention on the energy consumption issue related to on-chip global communication; this is especially true for data dominated applications such as video processing. Taking into account scaling effects a novel coupling-aware bus power model is used to investigate the statistical properties of video data collected in the system bus of a reference hardware/software H.263/MPEG-4 video coder architecture. The results of this analysis and the low complexity requirements drive the definition of a bus encoding scheme called CDSPBI (Coupling Driven Separated Partial Bus Invert), optimized ad-hoc for video data. A VLSI implementation of the coding circuits completes the work with an area/delay/power characterization that shows the effectiveness of the proposed scheme in terms of global power saving for a small circuit area overhead.

In this letter, a generalized extension of the linear Z4 space time (ST) code of [1] is conducted to obtain a linear Zw structure that can be flexibly used for various numbers of transmitter antennas, number of states, and modulation types. Additionally, the corresponding recursive systematic (RS) code structure is presented. The optimal code of the quadrature phase shift keying (QPSK) and 8 phase shift keying (PSK) modulation with 2 transmit antenna case is obtained from a code search and analyzed in comparison to the codes of [5]. Additionally, the structure for the 8, 32, and other number of states that were not provided in are [1] presented in this paper.

In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.

We propose a sophisticated synthesis methodology for SoC (System-on-Chip) architectures from the system level specification based on reusable high-level IPs named as Virtual Cores (VCores), in this paper. This synthesis methodology generates an initial architecture that consists of a CPU, buses, IPs, peripherals, I/Os and an RTOS (Real Time Operating System), as well as making tradeoffs to the architecture, between hardware and software on assigned software VCores and hardware VCores. The results of an architecture level design experiment, using the proposed methodology, shows that the partial automation of the architecture synthesis process, allied with design reuse, accelerates the architecture design, therefore, reducing the time required to design an architecture of SoC.

A SuperHTM embedded processor core implemented in a 130-nm CMOS process running at 400 MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW in worst-case conditions. It has a dual-issue seven-stage pipeline architecture but maintains the 1.8 MIPS/MHz of the previous five-stage processor. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems.

This paper presents a VLSI design methodology for the MAC-level DWT/IDWT processor based on a novel limited-resource scheduling algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of limited-resource FIR filtering has been developed for the scheduling of the MAC-level DWT/IDWT signal processing. Given a set of architecture constraints and DWT parameters, the scheduling algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation. Because the memory for the inter-octave is considered with the register of FIR filter, the memory size is less than the traditional architecture. Besides, based on the limited-resource scheduling algorithm, an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPs can be efficiently realized by tuning the parameters and applied for signal processing applications.

This paper presents a novel architecture to solve two problems of existing FPGAs : the large delay and area due to complex programmable switch blocks, and the large area due to coarse-grain logic blocks that are underutilized to a great degree. A mesh-connected cellular array based on a bit-serial pipeline architecture is introduced to minimize complexity of switch blocks. A fine-grain logic block architecture with a functionality of a bit-serial adder is presented to minimize the number of inputs and outputs of the logic block since increase in the number of inputs and outputs directly increases the complexity of a switch block. For an area-efficient design, the logic block is implemented based on a hybrid of a programmable logic gate and a dedicated carry logic. The hybrid architecture allows us to use a small lookup table to implement the logic gate. Moreover, the carry logic uses a functional pass-gate that merges both logic and storage functions compactly. The performance of the fine-grain field-programmable VLSI (FPVLSI) is evaluated to be more than 2 times higher than that of a coarse-grain FPVLSI.

A novel Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) architecture using the Multiple-Valued Source-Coupled Logic (MVSCL) is proposed to implement special-purpose processors. An MV-FPVLSI consists of identical cells, which are connected to 8-neighborhood ones. To reduce the complexity of the interconnection block between two cells in an MV-FPVLSI, a bit-serial fine-grain pipeline architecture is introduced which allows single-wire data transmission and as a result, the data-transmission delay becomes very small in comparison with that of a conventional FPGA. To reduce the number of switches in the interconnection block further, a cell, using multiple-valued source-coupled logic circuits, is proposed, where the input currents can be linearly summed just by wiring without using any active devices. Not only the data, but also the control signal can be superposed by linear summation. As a result, no input switch is required which contributes to smaller data transmission delay. Moreover, an arbitrary 2-input logic function can be generated by linear summation of the input currents and threshold operations using these reconfigurable MVSCL circuits. As the MVSCL circuit has high driving capability in comparison with that of an equivalent CMOS circuit, high-speed logic operation is also possible while maintaining low power.

We propose a novel hierarchical transmission method of DCT coefficients using multi-code DS/SS modulation. For low resolution image transmission over noisy channel, an error resilient and graceful degradation technique is necessary. Here, the DCT coefficients are divided into each stratum (a branch of multi-code DS/SS) and transmitted simultaneously through a noisy channel. By assigning an appropriate transmission energy that corresponds to their source energy variances, energy assignment, it is possible to maintain picture quality effectively even in a noisy channel. Analysis of this method was performed using an image data model, 2-D Gauss-Markov random field, which showed that picture quality is maintained even in the noisy channel condition.

A batch process is a typical concurrent system in which multiple interacting tasks are carried out in parallel on several batches at the same time. A major difficulty in designing a batch control system is the lack of modeling techniques. This paper aims at developing a method of constructing batch control system models in a hierarchical manner and operating batch processes using the constructed models. For this purpose, it first defines process and plant specifications described by partial languages, next presents a procedure for constructing hierarchical Petri net based models, and states the verification of models based on reachability analysis. It also discusses the detection of faults and conflicts in batch processes based on place-invariant analysis.

This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.

This paper proposes and theoretically evaluates two different schemes of code acquisition for pulse-position modulation (PPM) and overlapping PPM (OPPM) fiber-optic code-division multiple-access (CDMA) systems, namely threshold-based and demodulator-based code acquisition. Single-dwell detector and serial-search algorithm are employed for both schemes. Theoretical analysis is carried out for shot-noise-limited photon-counting receiver. Discussions upon effects of various parameter settings on the performance of code acquisition for PPM/OPPM fiber-optic CDMA systems, such as index of overlap, PPM/OPPM multiplicity, average photon counts per information nat, and darkcurrents, are presented. It is shown that when the threshold is properly selected, the threshold-based code acquisition system offers better performance, in terms of mean number of training frames, than the demodulator-based one.

The PN triangle method has a great significance in processing tessellation at the hardware level without software assistance. Despite its significance, however, the conventional PN triangle method has certain defects such as inefficient GE operation and degradation of visual quality. Because the method tessellates a curved surface according to the user-defined fixed LOD (Level Of Detail). In this paper, we propose adaptive tessellation of PN triangles using minimum-artifact edge linking. Through this method, higher efficiency of tessellation and better quality of scene are obtained by adaptivity and minimum-artifact edge linking, respectively. This paper also presents a hardware architecture of a PN triangle method using adaptive LOD, which is not a burden for overall 3D graphics hardware.

Three representative protocols are proposed to support mobility for IPv6 in IETF: Mobile IPv6, Hierarchical Mobile IPv6, and Fast Handovers for Mobile IPv6. Recently, IEEE 802.11 network has been widely deployed in public areas for mobile Internet services. In the near future, IPv6 mobility support over IEEE 802.11 network is expected to be a key function to actualize the pure IP-based mobile multimedia service. The IPv6 mobility support protocols have their characteristics in terms of signaling, handover latency, lost packets, and required buffer size. In this paper, we analyze the performance of the protocols over IEEE 802.11 network. We define a packet-level traffic model and a system and mobility model. Then, we construct a framework for the performance analysis. We also make cost functions to formalize each protocol's performance. Lastly, we investigate the effect of varying parameters used to show diverse numerical results.

Even in embedded processors, the accuracy in a branch prediction significantly affects the performance. In designing a branch predictor, in addition to accuracy, microarchitects should consider area, delay and power consumption. We propose two techniques to reduce the power consumption; these techniques do not requires any additional storage arrays, do not incur additional delay (except just one MUX delay) and never deteriorate accuracy. One is to look up two predictions at a time by increasing the width (decreasing the depth) of the PHT (Prediction History Table). The other is to reduce unnecessary accesses to the BTB (Branch Target Buffer) by accessing the PHT in advance. Analysis results with Samsung Memory Compiler show that the proposed techniques reduce the power consumption of the branch predictor by 15-52%.

Hierarchical Mobile IPv6 (HMIPv6) has been proposed to improve the performance capability of Mobile IPv6 at handover. In HMIPv6, local entities named Mobility Anchor Points (MAPs) are distributed throughout a network to localize the management of intra-domain mobility. In particular, multi-layered MAP has been proposed to improve performance. MAPs reduce the number of Binding Updates to the Home Agent and improve the communication quality at handover. These conventional methods that manage a multi-layered MAP cannot, however, select an appropriate MAP because they use the virtual mobility speed. As a result, they increase the signaling traffic in a multi-layered MAP. Moreover, they may cause the load to concentrate at a specific MAP. In this paper, we propose a location management method for Hierarchical Mobile IPv6 using the MN's mobile history. In this method, when a MN performs a handover, the Access Router calculates the area-covered rate of each upper MAP from the MN's mobile history and selects the MAP that best manages the MN in accordance with its rate. Thus, the proposed method reduces both the number of Binding Updates to the Home Agent and the signaling traffic because it reduces the frequency of changing the MAP. We evaluate the performance of the proposed method by simulation.

In December 2001, the authors started two kinds of experiments on the meteor burst communication (MBC) in Antarctica to study the ability of MBC as a communication medium for data collection systems in that region. In the first experiment, a continuous tone signal is transmitted from Zhongshan Station. The signal received at Syowa Station (about 1,400 km apart) is recorded and analyzed. This experiment is aimed to study basic properties of the meteor burst channel in that high latitude region. On the other hand, the second experiment is designed to estimate data throughput of a commercial MBC system in that region. A remote station at Zhongshan Station tries to transfer data packets each consisting of 10 data words to the master station at Syowa Station. Data packets are generated with five minutes interval. In this paper, we explain the experiments, briefly examine the results of the first year (from April 2002 to March 2003), and put forward the plan for the experiments in the second and third year. From the data available thus far, we can see that 1) the sinusoidal daily variation in the meteor activity typical in middle and low latitude regions can not be clearly seen, 2) non-meteoric propagations frequently dominate the channel especially during night hours, 3) about 60% of the generated data packets are successfully transferred to the master station within two hours delay even though we are now operating the data transfer system only for five minutes in each ten minutes interval, etc.

Hierarchical Mobile IPv6 (HMIPv6) has been proposed to manage the mobility of Mobile Terminals (MTs) hierarchically to reduce packet losses during local handover. HMIPv6 uses a mobility manageable router in a domain visited by the MTs to manage the micromobility of the MTs. The router is called Mobility Anchor Point (MAP). As a hierarchical mobility management scheme based on HMIPv6, we have already proposed a multilevel hierarchical distributed IP mobility management scheme to manage the mobility of MTs in a decentralized manner using multiple MAPs. Our scheme manages the mobility of an MT using a MAP having a suitable management domain. This usage of MAPs aims to efficiently decentralize the load of mobility management. Our scheme estimates the movement speed of the MT and then estimates the mobility of the MT based on the estimated movement speed of the MT to achieve the objective. However, recent simulation results obtained with more realistic mobility model indicate that our scheme has two problems in estimating the mobility of MTs: One is that our current scheme misestimates the movement speed of an MT in some cases, and the other is that our current scheme does not notice the changes in the mobility of an MT when the MT decelerates and stays in the same access area for a long time. Thus, an enhanced mobility estimation method is proposed in this paper. The enhanced method has an ability to estimate the movement speed of MTs more correctly and an ability to urge decelerated MTs to degrade their MAP quickly. Finally, the performance of the proposed mobility estimation method is evaluated using simulation experiments. The simulation results show that the enhanced method allows our scheme to estimate the mobility of MTs more correctly and so achieve more efficient load sharing.

Along with expansion of utilization of mobile ad hoc networks, it is expected that the network size becomes large. However, design of current typical routing protocols supposes at most several hop routes between source and destination nodes. When messages are delivered along long hop routes in the networks, such routing protocols tend to degrade performance. Previously, we have proposed an autonomous clustering scheme for constructing and maintaining hierarchical structure in mobile ad hoc networks, which are adaptive to node movement. This paper proposes a class of hierarchical routing protocols Hi-TORA, Hi-DSR and Hi-AODV, all of which are based on the autonomous clustering scheme, compares them with their corresponding flat routing protocols TORA, DSR and AODV, respectively, and shows effectiveness of these hierarchical routing protocols by simulation experiments.