In this paper, we propose two fast codebook generation algorithms for entropy-constrained vector quantization. The first algorithm uses the angular constraint to reduce the search area and to accelerate the search process in the codebook design. It employs the projection angles of the vectors to a reference line. The second algorithm has feature of using a suitable hyperplane to partition the codebook and image data. These algorithms allow significant acceleration in codebook design process. Experimental results are presented on image block data. These results show that our new algorithms perform better than the previously known methods.

This paper presents a new technique to implement a convolutional codec in VLSI. The code is used in the Trellis Code Modulation. The technique aims to reduce hardware complexity and increase throughput to decode the convolutional code using Viterbi algorithm. To simplify decoding algorithm and calculation, branch cost distances are pre-calculated and stored in a Distance Look Up Table (DLUT). By using the DLUT to get each branch cost in the algorithm, the hardware implementation of the algorithm does not require any calculation circuits. Furthermore, based on the trellis diagram, an Output Look-Up-Table (OLUT) is also constructed for decoding output generation. This table reduces the amount of storage in the algorithm. The use of look-up tables reduces hardware complexity and increases throughput of the decoder. Using this technique, a 16-states, radix-4 TCM codec with 2-D and 4-D was designed and implemented in both FPGA and ASIC after mathematically simulated. The tested ASIC has a core area of 1.1 mm2 in 0.18 µm CMOS technology and yields a decoding speed over 500 Mbps. Implementation results have shown that LUT can be used to decrease hardware requirement and to increase decoding speed. The designed codec can be used as an IP core to be integrated into system-on-chip applications and the technique can be explored to use to decode the turbo code.

This paper presents a cost-effective CORDIC-based architecture for adaptive lattice filters. An implementation method for an ARMA lattice filter using the CORDIC algorithm has been proposed. The previously proposed method can provide a simple filter architecture; however, it has problems such as redundant structure and numerical inaccuracy. Therefore, by solving each problem we derive a new non-redundant filter architecture with improved numerical accuracy. The obtained filter architecture provides a low cost ARMA lattice filter in which high-precision data processing is feasible. In addition, the proposed architecture can be applied to AR-type lattice filters, so that it may have several applications in adaptive signal processing. The presented filter architecture is useful from a hardware point of view because it facilitates an effective VLSI design of various adaptive lattice filters.

Most of system-on-chips (SOCs) have many memory cores. Diagnosis is often used to improve the yield of memories. Memory cores usually represent a significant portion of the chip area and dominate the yield of the chip. Memory diagnosis thus is one of key techniques for improving the yield and quality of SOCs. Content addressable memories (CAMs) are important components in many SOCs. In this paper we propose a three-phase diagnosis procedure for binary CAMs (BCAMs). The user can distinguish different types of BCAM-specific comparison and RAM faults and locate the faulty cells with the procedure. A March-like fault identification algorithm is also proposed. The algorithm can distinguish different types of faults--including typical RAM faults and BCAM-specific comparison faults. The algorithm requires 15N Read/Write operations and 2(N + B) Compare operations for an N B-bit BCAM. Analysis results show that the algorithm has 100% diagnostic resolution for the target faults.

Next-generation wireless/mobile networks will be IP-based cellular networks integrating Internet with the existing cellular networks. Recently, Hierarchical Mobile IPv6 (HMIPv6) was proposed by the Internet Engineering Task Force (IETF) for efficient mobility management. HMIPv6 reduces the amount of signaling and improves the performance of MIPv6 in terms of handoff latency. Although HMIPv6 is an efficient scheme, the performance of wireless networks is highly dependent on various system parameters such as user mobility model, packet arrival pattern, etc. Therefore, it is essential to analyze the network performance when HMIPv6 is deployed in IP-based cellular networks. In this paper, we develop two analytic models for the performance analysis of HMIPv6 in IP-based cellular networks, which are based on the random-walk and the fluid-flow models. Based on these analytic models, we formulate the location update cost and the packet delivery cost. Then, we analyze the impact of cell residence time and user population on the location update cost and the packet delivery cost, respectively. In addition, we study the variation of the total cost as the session-to-mobility ratio is changed and the optimal MAP domain size to minimize the total cost is also investigated.

A combination of slides used in a presentation and a video recording of the circumstances of the presentation are quite useful for many applications, such as e-learning. However, to create new content from these with current authoring tools requires considerable effort for the author and the products have reduced flexibility. In this paper, we propose the preparation of a unifying function without creating new content manually. We also propose a new approach to search unified presentation manuscripts for slides matched with given keywords by considering the features peculiar to the presentation slides. We propose impression indicators to express how well a slide matches the given keywords. We also propose a system for retrieving a sequence of desired presentation slides from archives of the combined slides and video. We named the system Unified Presentation Slide Retrieval by Impression Search Engine or UPRISE. We describe the system configuration of UPRISE and the experimentation undertaken to evaluate the effect of the proposed indicators and to compare the results with those of the traditional tf.idf retrieval method.

A novel design of Cerebellar Model Articular Controller (CMAC) is presented in this article. The controller is designed by means of a content addressable memory (CAM) to replace a hash-coding function, which is adopted by generic CMACs to tackle memory space problem how a large space maps into a small one. With a different address mapping method from hash-coding methods, each memory location of the proposed architecture includes two tuples: One is the conceptual address stored in a CAM, and another is the weight associated with the conceptual address stored in a SRAM. The CAM, with capability of fast comparison, is used to determine if any of CAM's content is identical to current conceptual address in parallel. If no match occurs, an associated mask function is triggered to expand searching range, which is centered by current conceptual address with a radius defined by the number of maskable bits. If a location in the CAM carries the similar address, the weight (in SRAM) related to this matching location would be shared and updated by both the current conceptual address and the conceptual address in this location. Therefore, the control noises caused by hash-coding methods can be attenuated significantly in either the training or the recall phases in the proposed architecture. Furthermore, if there is no match in current search, after the mask function is executed, the new conceptual address with an initial weight value would be stored in a CAM cell sequentially indexed by an incremental pointer. Instead of storing the information by scattering it over the memory, the proposed architecture sequentially stores the information by the index of this pointer to increase the memory utilization. Simulation results, (1) one input variable and two input variables cases of function approximations, (2) a truck backer-upper control, demonstrate the plausible performance of the proposed CMAC architecture. The architecture and the design criteria for the proposed controller are also discussed.

In a content-based image retrieval (CBIR) system, both the retrieval relevance and the response time are very important. This letter presents the condensed two-stage search method as a new fast image retrieval approach by making use of the property of Cauchy-Schwarz inequality. The method successfully reduces the overall processing time for similarity computation, while maintaining the same retrieval relevance as the conventional exhaustive search method. By the extensive computer simulations, we observe that the condensed two-stage search method is more effective as the number of images and dimensions of the feature space increase.

The deployment of server replicas of a service across an asynchronous distributed system (e.g., Internet) is a real practical challenge. This target cannot be indeed achieved by classical software replication techniques (e.g., passive and active replication) as these techniques usually rely on group communication toolkits that require server replicas to run over a partially synchronous distributed system to solve the underlying agreement problem. This paper proposes a three-tier architecture for software replication that encapsulates the need of partial synchrony in a specific software component of a mid-tier to free replicas and clients from the need of underlying partial synchrony assumptions. Then we propose how to specialize the mid-tier in order to manage active replication of server replicas.

Interest in the regulatory issues for Software Defined Radio (SDR) is spreading worldwide since the Federal Communications Commission (FCC) recently recognized SDR and created a new category for SDR authorization. SDR technology will bring enormous benefits to the field of wireless services. However, in order to ensure such benefits, revisions of the radio law and/or related ordinances are required regardless of standardization of the software downloading and other implementation details. In order to define the issues peculiar to SDR and to investigate how conformity evaluation should be conducted for radio equipments whose RF characteristics can be altered by software changes in the field, "Study Group on Software Technology for Radio Equipment" was organized by the Telecom Engineering Center (TELEC) in 2000. This paper summarizes a report of the Study Group that was published in March 2003 including the proposal for "Technical regulation conformity evaluation system," the principal output of the study, which proposes how to prevent unauthorized changes to radio equipment in the field.

The E-1-track switch torus array model and the "EAR" reconfiguration method are proposed for fault tolerance of mesh or torus-connected processor arrays, where the original idea of EAR is in EAM. The comparison among these and others is described in terms of the (run-time) array reliability, hardware overhead, and/or reconfiguration time. When a designer chooses one among fault tolerant methods, he should consider their features synthetically case by case, and we consider that the results given by this paper are useful for the choice.

A novel reconfigurable architecture has been proposed for a mobile terminal receiver that can drastically reduce power dissipation dependant on adjacent channel interference. The proposed design can automatically scale the number of filter coefficients and word length respectively by monitoring the in-band and out-of-band powers. The new architecture performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. The UTRA-TDD downlink mode was examined statistically and results show that the reconfigurable architectures can save an average of up to 75% power dissipation respectively when compared to a fixed filter length of 57 and word length of 16 bits. This power saving only applies to the filter and ADC, not the whole receiver. This will prolong talk and standby time in a mobile terminal. The average number of taps and bits were calculated to be 14.98 and 10 respectively, for an outage of 97%.

This paper proposes a test generation method using several partly compacted test plan tables for RTL data paths. Combinational modules in data paths are tested using several partly compacted test plan tables. Each partly compacted test plan table is generated from each grouped test plan set and is used to test combinational modules corresponding to the grouped test plans. The values of control signals in a partly compacted test plan table are supplied by a test controller. This paper also proposes the architecture of a test controller which can be synthesized in a reasonable amount of time, and proposes a test plan grouping method to shorten test length for data paths under a test controller area constraint. Experimental results for benchmarks show that the test lengths are shortened by 4 to 36% with -9 to 8% additional test controller area compared with the test generation method using test plans.

Nowadays, the use of dependable systems is generalising, and diagnosis is an important step during their design . A diagnosis in early phases of the design cycle allows to save time and money. Fault injection can be used during the design process of the system, and using Hardware Description Languages, particularly VHDL, it is possible to accomplish this early diagnosis. During last years, the Time-Triggered Architecture (TTA) has emerged as a hard real-time fault-tolerant architecture for embedded systems. This novel architecture is gaining adepts mainly in the avionics and automotive industries ( x-by-wire ). The TTA implements a synchronous protocol with static scheduling that has been specifically targeted at hard real-time fault-tolerant distributed system. In this work, we present the study of the VHDL model of a communication controller based on the TTA, where a number of fault injection campaigns have been carried out. We comment the results produced and suggest some solutions to problems detected.

A high-speed 3-D camera has a future possibility of wide variety of application fields such as quick inspection of industrial components, observation of motion/destruction of a target object, and fast collision prevention. In this paper, a row-parallel position detector for a high-speed 3-D camera based on a light-section method is presented. In our row-parallel search method, the positions of activated pixels are quickly detected by a row-parallel search circuit in pixel and a row-parallel address acquisition of O(log N) cycles in N-pixel horizontal resolution. The architecture keeps high-speed position detection in high pixel resolution. We have designed and fabricated the prototype position sensor with a 12816 pixel array in 0.35 µm CMOS process. The measurement results show it achieves quick activated-position acquisition of 450 ns for "beyond-real-time" 3-D imaging and visual feedback. The high-speed position detection of the scanning sheet beam is demonstrated.

A fast winner search method based on separating all codewords in the original codebook completely into a promising group and an impossible group is proposed. Group separation is realized by using sorted both L1 and L2 norms independently. As a result, the necessary search scope that guarantees full search equivalent PSNR can be limited to the common part of the 2 individual promising groups. The high search efficiency is confirmed by experimental results.

Holonic Manufacturing Systems (HMSs), in which decisions are made through cooperation among holons (autonomous and cooperative manufacturing entities), eliminate various bottlenecks that exist in conventional systems to adapt to high-variety low-volume production. This paper describes the architecture of HMSs. Issues regarding incremental development and dynamic reconfiguration of cooperation mechanisms themselves, and mechanisms for ensuring stable and safe behaviors of HMSs are also discussed with reference to several proposals, with a view to applying the HMS architecture to large and complicated applications.

In this paper, a new Hierarchical Sum of Double Difference metric, HSDD, is introduced. It is shown, as opposed to conventional Sum of Absolute Difference (SAD) metric, how this zerotree coding aware metric can jointly constrain the motion vector searching for both temporal and spatial (quad-tree) directions under multiresolution motion estimation framework. The reward from the temporal-spatial co-optimization concept of HSDD is that fewer bits are spent later for describing the isolated zeros. The embedded wavelet video coder using HSDD metric was tested with a set of video sequences and the compression performance seems to be promising.

In this letter, we propose (1) a new sub-optimum minimum distance search (sub-MDS), whose search complexity is reduced considerably compared with optimum MDSs and (2) a termination criterion, called near optimality condition, to reduce the average number of decoding iterations with little degradation of error performance for the proposed decoding using sub-MDS iteratively. Consequently, the decoding algorithm can be applied to longer codes with feasible complexity. Simulation results for several Reed-Muller (RM) codes of lengths 256 and 512 are given.

In this paper, we introduce a flexible design for intellectual property(IP) which has become important to design system LSI. The proposed IPs which have high flexibility for user requirement. The design priority is determined by setting parameters as the number of arithmetic unit, internal bitlength, clock speed and so on. The design time can thus be reduced. Designed IP is based on the reconfigurable architecture in which many structures can be dynamically selected. This paper shows a implementation of Frequency Response Masking digital filter(FRM) and Principal Components Analysis(PCA) using a reconfigurable architecture. We show the method to realize the designed circuit and the results of experiments using field programmable gate array(FPGA).