In this paper we propose a parallel and distributed computation of genetic local search with irregular topology in distributed environments. The scheme we propose in this paper is implemented with a tree topology established on an irregular network where each computing element carries out genetic local search on its own chromosome set and communicates with its parent when the best solution of each generation is updated. We evaluate the proposed algorithm by a simulation system implemented on a PC-cluster. We test our algorithm on four types topologies: star, line, balanced binary tree and sided binary tree, and investigate the influence of communication topology and delay on the evolution process.

DNA Sequence Design Problem is a crucial problem in information-based biotechnology such as DNA computing. In this paper, we introduce a powerful design strategy for DNA sequences by refining Random Generator. Random Generator is one of the design strategies and offers great advantages, but it is not a good algorithm for generating a large set of DNA sequences. We propose a Two-Step Search algorithm, then show that TSS can generate a larger set of DNA sequences than Random Generator by computer simulation.

Applying the formerly proposed classification framework for first order line search optimization techniques we introduce novel superlinear first order line search methods. Novelty of the methods lies in the line search subproblem. The presented line search subproblem features automatic step length and momentum adjustments at every iteration of the algorithms realizable in a single step calculation. This keeps the computational complexity of the algorithms linear and does not harm the stability and convergence of the methods. The algorithms have none or linear memory requirements and are shown to be convergent and capable of reaching the superlinear convergence rates. They were practically applied to artificial neural network training and compared to the relevant training methods within the same class. The simulation results show satisfactory performance of the introduced algorithms over the standard and previously proposed methods.

Sampling is important for many applications in research areas such as graphics, vision, and image processing. In this paper, we present a novel stratified sampling algorithm (SSA) for the coiled tubing surface with a given probability density function. The algorithm is developed from the inverse function of the integration for the areas of the coiled tubing surface. We exploit a Hierarchical Allocation Strategy (HAS) to preserve sample stratification when generating any desirable sample numbers. This permits us to reduce variances when applying our algorithm to Monte Carlo Direct Lighting for realistic image generation. We accelerate the sampling process using a segmentation technique in the integration domain. Our algorithm thus runs 324 orders of magnitude faster when using faster SSA algorithm where the order of the magnitude is proportional to the sample numbers. Finally, we employ a parabolic interpolation technique to decrease the average errors occurred for using the segmentation technique. This permits us to produce nearly constant average errors, independent of the sample numbers. The proposed algorithm is novel, efficient in computing and feasible for realistic image generation using Monte Carlo method.

This paper presents a network architecture with a dual interface IP handoff technique that allows smooth node mobility without using any intermediate proxy. The proposed architecture is suitable for low bit-rate time sensitive real time applications, where payload tends to be short and packet header overhead is particularly significant. Connections are established as per permanent addresses of the nodes but are carried on by the IP layer according to the temporary addresses by address translation within the end hosts. The mapping information is maintained by database servers, which can be placed in the Internet in a distributed manner. We describe the architecture and show its mobile capabilities by prototype implementation and performance evaluation. Furthermore a dual-interface handoff suitable to the proposed architecture is also introduced. Preliminary results show that the proposed architecture has significantly low overheads. It is compatible with the existing infrastructure and works fine in both IPv4 and IPv6 environments. Analysis also shows that with dual-interface handoff it is possible to achieve seamless handoff without any packet loss by exploiting overlapping coverage area and speed of the mobile node. Handoff latency is reduced significantly as compare to MIPv6. We believe that with more powerful network interface card drivers our concept of dual interface handoff can be realized.

Learning behaviors of hierarchically structured stochastic automata operating in a general nonstationary multiteacher environment are considered. It is shown that convergence with probability 1 to the optimal path is ensured by a new learning algorithm which is an extended form of the relative reward strength algorithm. Several computer simulation results confirm the effectiveness of the proposed algorithm.

In mobile multimedia environment, it is very important to minimize handoff latency due to mobility. In terms of reducing handoff latency, Hierarchical Mobile IPv6 (HMIPv6) can be an efficient approach, which uses a mobility agent called Mobility Anchor Point (MAP) in order to localize registration process. However, MAP can be a single point of failure or performance bottleneck. In order to provide mobile users with satisfactory quality of service and fault-tolerant service, it is required to cope with the failure of mobility agents. In, we proposed Robust Hierarchical Mobile IPv6 (RH-MIPv6), which is an enhanced HMIPv6 for fault-tolerant mobile services. In RH-MIPv6, an MN configures two regional CoA and registers them to two MAPs during binding update procedures. When a MAP fails, MNs serviced by the faulty MAP (i.e., primary MAP) can be served by a failure-free MAP (i.e., secondary MAP) by failure detection/recovery schemes in the case of the RH-MIPv6. In this paper, we investigate the comparative study of RH-MIPv6 and HMIPv6 under several performance factors such as MAP unavailability, MAP reliability, packet loss rate, and MAP blocking probability. To do this, we utilize a semi-Markov chain and a M/G/C/C queuing model. Numerical results indicate that RH-MIPv6 outperforms HMIPv6 for all performance factors, especially when failure rate is high.

Braids have been studied by mathematicians for more than one century. Because they are so practical as to be used for cryptography, many cryptographers have been interested in them. For the last five years, there have been proposed some cryptographic applications and cryptanalyses in the area of braids. We survey the main examples of these results.

This paper investigates some fundamental properties of one-way alternating pushdown automata with sublinear space. We first show that one-way nondeterministic pushdown automata are incomparale with one-way alternating pushdown automata with only universal states, for spaces between log log n and log n, and also for spaces between log n and n/log n. We then show that there exists an infinite space hierarchy among one-way alternating pushdown automata with only universal states which have sublinear space.

In this paper, we describe how to exploit a machine-readable dictionary (MRD) and domain-specific text corpus in supporting the construction of domain ontologies that specify taxonomic and non-taxonomic relationships among given domain concepts. In building taxonomic relationships (hierarchical structure) of domain concepts, some hierarchical structure can be extracted from a MRD with marked subtrees that may be modified by a domain expert, using matching result analysis and trimmed result analysis. In building non-taxonomic relationships (specification templates) of domain concepts, we construct concept specification templates that come from pairs of concepts extracted from text corpus, using WordSpace and an association rule algorithm. A domain expert modifies taxonomic and non-taxonomic relationships later. Through case studies with "the Contracts for the International Sales of Goods (CISG)" and "XML Common Business Library (xCBL)", we make sure that our system can work to support the process of constructing domain ontologies with a MRD and text corpus.

The modeling of an application domain and its specific knowledge description language are important for developing knowledge-based systems. A rapid-prototyping approach is suitable for such developments since in this approach the modeling and language development are processed simultaneously. However, programming languages and their supporting environments which are usually used for prototyping are not necessarily adequate for developing practical applications. We have been developing an integrated development environment for knowledge-based systems, which supports all the development phases from the early prototyping phase to final commercial development phase. The environment called INSIDE is based on a Prolog abstract machine, and provides all of the functions required for the development of practical applications in addition to the standard Prolog features. This enables the development of both prototypes and practical applications in the same environment. Moreover, their efficient development and maintenance can be achieved. In addition, the effectiveness of INSIDE is described by examples of its practical application.

Online shopping is becoming more and more popular in recent years. However, users are still unable to find what they want on the online market very efficiently. In our previous paper we suggested a system that helps to find short-sleeved T-shirts for young women on the online market. Then we conducted several verification experiments and proved that the system was effective. In this paper, we modified the system by adopting the following schemes in order to make it more versatile; First, all information is presented in a unified format. Second, users are provided with multiple-choice key words. Third, users search results are used to select information that is truly useful for the user. Lastly, we conducted several verification experiments and proved that these schemes were effective.

We apply a selective-sets resizable cache and a complete hierarchy SRAM for the high-performance and low-power RISC CPU core. The selective-sets resizable cache can change the cache memory size by varying the number of cache sets. It reduces the leakage current by 23% with slight degradation of the worst case operating speed from 213 MHz to 210 MHz. The complete hierarchy SRAM enables the partial swing operation not only in the bit lines, but also in the global signal lines. It reduces the current consumption of the memory by 4.6%, and attains the high-speed access of 1.4 ns in the typical case.

A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.

In this letter, we propose a groupwise successive interference cancellation (GSIC) receiver with gradient descent search for multi-rate DS-CDMA system. Proposed receiver incorporates iterative gradient descent search algorithm into conventional GSIC receiver for multi-rate DS-CDMA system. It is shown that the receiver achieves significant performance improvement over the matched filter (MF) receiver, GSIC receiver, multi-stage parallel interference cacnellation (PIC) receiver, multi-stage partial PIC receiver, and GSIC receiver with PIC in a Rayleigh fading channel.

A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multi-datapath radix-23 computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.82.8 mm2 with CMOS 0.35 µm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensonal FFT in 23.2 µsec and a 2-dimensional one in only 23.8 msec at 133 MHz operation. The power consumption of this processor is 439.6 mW at 3.3 V, 100 MHz operation.

Viterbi search engine in speech recognition consumes many computation time and hardware resource for finding maximum likelihood in HMM (Hidden Markov Model). We propose a fast Viterbi search engine using IHMM (Inverse Hidden Markov Model). A benefit of this method is that we can remove redundant computation of path matrix. The power consumption and the computational time are reduced by 68.6% at the 72.9% increase in terms of the number of gates.

Conventional vector quantization (VQ) encoding method by full search (FS) is very heavy computationally but it can reach the best PSNR. In order to speed up the encoding process, many fast search methods have been developed. Base on the concept of multi-resolutions, the FS equivalent fast search methods using mean-type pyramid data structure have been proposed already in. In this Letter, an enhanced sum pyramid data structure is suggested to improve search efficiency further, which benefits from (1) exact computing in integer form, (2) one more 2-dimensional new resolution and (3) an optimal pair selecting way for constructing the new resolution. Experimental results show that a lot of codewords can be rejected efficiently by using this added new resolution that features lower dimensions and earlier difference check order.

Next-generation wireless/mobile networks will be IP-based cellular networks integrating Internet with the existing cellular networks. Recently, Hierarchical Mobile IPv6 (HMIPv6) was proposed by the Internet Engineering Task Force (IETF) for efficient mobility management. HMIPv6 reduces the amount of signaling and improves the performance of MIPv6 in terms of handoff latency. Although HMIPv6 is an efficient scheme, the performance of wireless networks is highly dependent on various system parameters such as user mobility model, packet arrival pattern, etc. Therefore, it is essential to analyze the network performance when HMIPv6 is deployed in IP-based cellular networks. In this paper, we develop two analytic models for the performance analysis of HMIPv6 in IP-based cellular networks, which are based on the random-walk and the fluid-flow models. Based on these analytic models, we formulate the location update cost and the packet delivery cost. Then, we analyze the impact of cell residence time and user population on the location update cost and the packet delivery cost, respectively. In addition, we study the variation of the total cost as the session-to-mobility ratio is changed and the optimal MAP domain size to minimize the total cost is also investigated.

A new algorithm and architecture to eliminate redundant operations in block-matching (BM) motion estimation is proposed. The key step of this work is to use binary-matching to define image regions with the static background content and then exclude these regions from the actual motion estimation. According to experiments, the approach maintains the highest PSNR, while making as half as less computations in comparison to the adaptive BM or 1/8 of the computations required by the full-search BM. An implementation scheme is outlined.