Micromobility management is a key issue for the deployment of broadband mobile communication services. The packet loss during handover and the handover latency need to be minimized to maintain the high quality of these services. We have previously proposed a mobility management scheme that addresses this issue in wide-area mobile networks that employed hierarchical multiple mobility management routers (Mobility Anchor Points or MAPs). Our scheme directs a Mobile Terminal (MT) to a suitable MAP to fully minimize packet loss during handover, and handover latency of the MTs. In our previous work, we confirmed the effectiveness of our scheme using a simple tree network. Actual networks however, always have densely meshed topologies to provide some redundancy for the elimination of single points of failure. In such networks, it is difficult to deduce the relationships between the MAPs, and this makes it difficult for our scheme to select a suitable MAP for an MT, because the selection is performed using both the MT's smoothed speed and the relationships existing between the MAPs located above the Access Router (AR), to which the MT is connected. In this paper, we propose a method to overcome this problem, by autonomously adjusting the selection criteria that are individually configured for use at a particular AR, and we evaluate this method using simulation experiments. The results show that our mobility management scheme works well in densely meshed networks using the proposed additional method.

This paper presents a method for tuning the structure of a causal network (CN) to evaluate a learner's profile for a learning assistance system that employs hierarchically structured learning material. The method uses as an initial CN structure causally related inter-node paths that explicitly define the learning material structure. Then, based on this initial structure other inter-node paths (sideway paths) not present in the initial CN structure are inferred by referring to the learner's database generated through the use of a learning assistance system. An evaluation using simulation indicates that the method has an inference probability of about 63% and an inference accuracy of about 30%.

The hand posture estimation system by searching a similar image from a vast database, such as our previous research, may cause the increase of processing time, and prevent realtime controlling of a robot. In this study, the authors proposed a new estimation method of human hand posture by rearranging a large-scale database with the Self-Organizing Map including self-reproduction and self-annihilation, which enables two-step searches of similar image with short period of processing time, within small errors, and without deviation of search time. The experimental results showed that our system exhibited good performance with high accuracy within processing time above 50 fps for each image input with a 2.8 GHz CPU PC.

Real-time object detection or recognition technology becomes more important for various intelligent vision systems. Processing models for object detection or recognition from natural images should tolerate pattern deformations and pattern position shifts. The hierarchical convolutional neural networks are considered as a promising model for robust object detection/recognition. This model requires huge computational power for a large number of multiply-and-accumulation operations. In order to apply this model to robot vision or various intelligent real-time vision systems, its LSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose an LSI architecture based on this algorithm. As a proof of concept for our LSI architecture, we have designed, fabricated and tested two test LSIs: a sorting LSI and an image-filtering LSI. The sorting LSI is designed based on the content addressable memory (CAM) circuit technology. The image-filtering LSI is designed for parallel processing by analog circuit array based on the merged/mixed analog-digital approach. We have verified the validity of our LSI architecture by measuring the LSIs.

This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one scan chain is active during scan test. Therefore, both average power and peak power are reduced compared with conventional full scan test methodology. This paper also proposes a tabu search-based approach to minimize test application time. In this approach we handle the information during deterministic test efficiently. Experimental results demonstrate that this approach drastically reduces both average power and peak power dissipation at a little longer test application time on various benchmark circuits.

This paper describes the efficiency of VLSI architecture for UMHexagonS (hybrid Unsymmetrical cross Multi Hexagon grid Search) matching algorithm. This algorithm is used for ME (Motion Estimation) of H.264/AVC video compression standard. The UMHexagonS is called a hybrid algorithm since it uses different kinds of searching patterns. VLSI architecture based on UMHexagonS is designed to provide a good tradeoff between gate sizes and high throughput. We implemented this architecture with about 309 K gates and 1/1792 throughput [block/cycle] for a search range of 16 and 44 macro blocks using synthesizable Verilog HDL.

A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.

We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 16032 dual-port SRAM using 0.25 µm standard cell technology. This circuit can process 88 image frames with 1,280720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.

The fast handover protocol adopted in a IPv6 hierarchical structure provides a seamless handover in wireless IP networks by minimizing the handover latency. To reduce the handover latency, the fast handover uses anticipation based on layer 2 trigger. Nonetheless, a mobile node can still lose its connection with the old link during the fast handover procedures. Accordingly, this paper analyzes the handover latency and packet delivery costs associated with fast handover failure cases based on a timing diagram.

We have developed an open-architecture router (OAR) prototype using industrial standard hardware, software components, and interfaces. The prototype is built with Advanced Telecom Computing Architecture (ATCA)-compliant hardware. Carrier-grade Linux (CGL) is used as the operating system. A new OAR configuration method is described where industrial standard hardware and software interfaces are used. Basic forwarding functions with routing protocol processing are demonstrated for the first time.

Researchers have proposed numerous approaches to providing Quality-of-Service (QoS) across the Internet. The IETF has proposed two reservation approaches: hop-by-hop bandwidth reservation (IntServ); and per-hop behaviour bandwidth reservation (DiffServ). An edge router generates traffic, accepts per-flow reservation and classifies them into predetermined service class; while a core router ensures different QoS guarantees for each service class. We propose an Edge-to-Edge Quality-of-Service Domain in which packet trains with the same service requirements aggregated using packet deadline at edge router. The properties of a packet train like Inter-Packet Departure Time, Inter-flow Departure Time and accumulated packet delay are embedded and used by our quantum-based scheduler and QoS packet forwarding scheme in core routers. Thus, we are able to extract per-queue and per-flow information. Each queue is reconstructed at core router with packets having an expected departure time that is relative to the ingress router. Useful functions like instantaneous service rate and fine granular dropping scheme can be derived with a combination of embedded information and relative virtual clock technique. The encapsulation of our packet train information converges mathematically. Through simulations, we show that our architecture can provide delay and rate guarantees and minimise jitter for QoS-sensitive flows that requires LR-coupled or LR-decoupled reservations.

Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows, a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 44 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of MN pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 µm CMOS technology. The core area is 2.13 mm1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25).

A cell search technique utilizing a known postfix for OFDM (orthogonal frequency division multiplexing) cellular systems is described. The known postfix is generated in the time domain by inserting pilots in the frequency domain and plays the role of the cyclic prefix in general OFDM systems. Since it demonstrates good correlation properties, it can be facilitated to synchronize each symbol with an identified postfix. In this paper, two different known postfixes are allocated to each cell. One is used for cell identification and symbol synchronization, which is designed to be different among neighboring cells. The other is used for frame synchronization and is the same for all cells. In the simulation, the cell search is accomplished with a probability greater than 10-3 at -27 dB in a vehicular channel. Even at -30 dB, the cell search probability is greater than 10-2 in a pedestrian channel as well as 10-3 in the AWGN (additive white gaussian noise) channel.

We address the problem of dealing with large collections of data, and investigate the use of automatically constructing domain specific category hierarchies to improve text classification. We use two well-known techniques, the partitioning clustering method called k-means and loss function, to create the category hierarchy. The k-means method involves iterating through the data that the system is permitted to classify during each iteration and construction of a hierarchical structure. In general, the number of clusters k is not given beforehand. Therefore, we used a loss function that measures the degree of disappointment in any differences between the true distribution over inputs and the learner's prediction to select the appropriate number of clusters k. Once the optimal number of k is selected, the procedure is repeated for each cluster. Our evaluation using the 1996 Reuters corpus, which consists of 806,791 documents, showed that automatically constructing hierarchies improves classification accuracy.

An improved algorithm for fast motion estimation based on the block matching algorithm (BMA) is presented for use in a block-based video coding system. To achieve enhanced motion estimation performance, we propose an adaptive search pattern length for each iteration for the current macro block (MB). In addition, search points that must be checked are determined by means of directional information from the error surface, thus reducing intermediate searches. The proposed algorithm is tested with several sequences and excellent performance is verified.

In this paper, we introduce a new method for depth perception from a 2D natural scene using scale variation of patterns. As the surface from a 2D scene gets farther away from us, the texture appears finer and smoother. Texture gradient is one of the monocular depth cues which can be represented by gradual scale variations of textured patterns. To extract feature vectors from textured patterns, higher order local autocorrelation functions are utilized at each scale step. The hierarchical linear discriminant analysis is employed to classify the scale rate of the feature vector which can be divided into subspaces by recursively grouping the overlapped classes. In the experiment, relative depth perception of 2D natural scenes is performed on the proposed method and it is expected to play an important role in natural scene analysis.

This paper presents a shortest path search algorithm using a model of excitable reaction-diffusion dynamics. In our previous work, we have proposed a framework of Digital Reaction-Diffusion System (DRDS)--a model of a discrete-time discrete-space reaction-diffusion system useful for nonlinear signal processing tasks. In this paper, we design a special DRDS, called an "excitable DRDS," which emulates excitable reaction-diffusion dynamics and produces traveling waves. We also demonstrate an application of the excitable DRDS to the shortest path search problem defined on two-dimensional (2-D) space with arbitrary boundary conditions.

An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables high-throughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for CIF 30 fr/s with 189 MHz clock frequency. Its estimated core size is 6.025.33 mm2 with six-metal 90-nm CMOS technology.

The shape-based routing needs a routing architecture with a geometrical computation framework on it. This paper introduces a novel routing architecture, Oct-Touched Tile (OTT), with a geometrical computation method along the horizontal- and vertical-constraints. The architecture is represented by the tiles spreading over the 2-D plane. Each tile is flexible to satisfy the constraints imposed for non-overlapping and sizing request. In this framework, path finding and shape-based sizing are executed on the same architecture. In experiments, our system demonstrates the performance comparable to a commercial tool. In addition, we show potential of OTT by introducing several ideas of extensions to analog layout constraints.

Genetic algorithms are a general problem-solving technique that has been widely used in computational biology. In this paper, we present a framework to map hierarchical parallel genetic algorithms for protein folding problems onto computational grids. By using this framework, the two level communication parts of hierarchical parallel genetic algorithms are separated. Thus both parts of the algorithm can evolve independently. This permits users to experiment with alternative communication models on different levels conveniently. The underlying programming techniques are based on generic programming, a programming technique suited for the generic representation of abstract concepts. This allows the framework to be built in a generic way at application level and thus provides good extensibility and flexibility. Experiments show that it can lead to significant runtime savings on PC clusters and computational grids.