In this paper, we propose a new computer-aided diagnosis system which can extract specific features from hematoxylin and eosin (HE)-stained breast tumor images and evaluate the type of tumor using artificial organisms. The gene of the artificial organisms is defined by three kinds of texture features, which can evaluate the specific features of the tumor region in the image. The artificial organisms move around in the image and investigate their environmental conditions during the searching process. When the target pixel is regarded as a tumor region, the organism obtains energy and produces offspring; organisms in other regions lose energy and die. The searching process is iterated until the 30th generation; as a result, tumor regions are filled with artificial organisms. Whether the detected tumor is benign or malignant is evaluated based on the combination of selected genes. The method developed was applied to 27 test cases and the distinction between benign and malignant tumors by the artificial organisms was successful in about 90% of tumor images. In this diagnosis support system, the combination of genes, which represents specific features of detected tumor region, is selected automatically for each tumor image during the searching process.

The forward link capacity plane of a hierarchically structured cellular CDMA system, in which a single frequency band is used for both macrocell and microcell layers, is obtained for isolated microcells (hotspots). The impact of each neighbour microcell and macrocell on the capacity plane, for a reference mobile station as the worst case, is also investigated. The results for the case of three microcells in each macrocell show that 69% of macrocell interference to microcell mobile stations comes from the closest macrocell. It is also found that 80% of macrocell interference to the reference macrocell mobile station comes from the central cell and the first cell tier around it.

The one dimensional cutting stock problem (1D-CSP) is one of the representative combinatorial optimization problems, which arises in many industries. As the setup costs of cutting patterns become more dominant in recent cutting industry, we consider a variant of 1D-CSP, in which the total number of applications of cutting patterns is minimized under the constraint that the number of different cutting patterns is specified in advance. We propose a local search algorithm that uses the neighborhood obtained by perturbating one cutting pattern in the current set of patterns, where the perturbations are done by utilizing the dual solution of the auxiliary linear programming problem (LP). In this process, in order to solve a large number of LPs, we start the criss-cross variation of the simplex algorithm from the optimal simplex tableau of the previous solution, instead of starting it from scratch. According to our computational experiment, it is observed that the proposed algorithm obtains a wide variety of good solutions which are comparable to the existing heuristic approaches.

Reconfigurable architectures have been focused for its potential on achieving high performance by reconfiguring special purpose circuits for a target application and its flexibility due to its ability of reconfiguring. We have set our sights on use of a reconfigurable architecture as a general-purpose computer by extending the advantageous properties of the architecture. To achieve the goal, a generalized execution model for reconfigurable architecture is required, so we have proposed an Ideal PARallel Structure (I-PARS) execution model. In the I-PARS execution model, any programs based on its model has no restriction depending on hardware structures based on a specific reconfigurable processor, which makes it easier to develop software. Further, we have proposed a PARS architecture which executes programs based on the I-PARS execution model effectively. The PARS architecture has a large reconfigurable part for highly parallel execution, which utilizes parallelism described on the I-PARS execution model. For effective utilization of the reconfigurable part in the PARS architecture, it has an ability to reconfigure and execute operations simultaneously in one cycle. Further, the PARS architecture supports branch operations to introduce control flow in an execution on the architecture, which makes it possible to skip an execution which does not produce a valid result. In this paper, we introduce the detailed structure of an implemented prototype processor based on the PARS architecture. In the implementation, 420,377 CMOS transistors were used, which was only 3.8% of the number of transistors used in the UltraSPARC-III in logic circuits. Additionally, we evaluated the performance of the prototype processor by using some benchmark programs. From the evaluation results, we found that the prototype processor could achieve nearly the same performance and be implemented with extremely the less number of transistors compared with UltraSPARC-III 750MHz.

This paper describes an ultra low power, motion estimation (ME) processor for MPEG2 HDTV resolution video. It adopts a Gradient Descent Search (GDS) algorithm that drastically reduces required computational power to 6 GOPS. A SIMD datapath architecture optimized for the GDS algorithm decreases the clock frequency and operating voltage. A low power 3-port SRAM with a write-disturb-free cell array arrangement is newly designed for image data caches of the processor. The proposed ME processor contains 7-M transistors, integrated in 4.50 mm 3.35 mm area using 0.13 µm CMOS technology. Estimated power consumption is less than 100 mW at 81 MHz@1.0 V. The processor is applicable to a portable HDTV system.

A fast-motion-estimation (ME) algorithm called a "breaking-off-search (BOS)" was developed. It can improve processing speed of the full-search (FS) method by a factor of 3.4. The BOS algorithm can not only sometimes achieve better visual quality than FS, but can also solve visual degradation problems associated with conventional fast-ME algorithms whenever picture patterns change (i. e. , presence of scene changes). The power dissipation of a 0.6-µ m CMOS parallel Wallace-tree motion estimator using BOS was reduced to about 281 mW which was 1/28.7 that of the 0.6-µ m CMOS binary-tree motion estimator using FS.

A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.

In this paper, we propose two channel allocation schemes for supporting voice and multimedia traffic in hierarchical cellular systems. They are guaranteed to satisfy the required quality of service for multimedia traffic in accordance with their characteristics such as a mobile velocity for voice calls and a delay tolerance for multimedia calls. In the first, only slow-speed voice calls are allowed to overflow from macrocell to microcell and only adaptive multimedia calls can overflow from microcell to macrocell after reducing their bandwidth to the minimum channel bandwidth. In the second, in addition to the first scheme, non-adaptive multimedia calls can occupy the required channel bandwidth through reducing the channel bandwidth of adaptive multimedia calls. The proposed schemes are analyzed using the 2-dimensional Markov model. Through computer simulations, it is shown that the proposed schemes yield a significant improvement in terms of the forced termination probability of handoff calls. In particular, the second decreases the blocking probability of new calls as well as the forced termination probability of handoff calls.

This paper proposes a gesture recognition method which uses higher order local autocorrelation (HLAC) features extracted from PARCOR images. To extract dominant information from a sequence of images, we apply linear prediction coding technique to the sequence of pixel intensities and PARCOR images are constructed from the PARCOR coefficients of the sequences of the pixel values. From the PARCOR images, HLAC features are extracted and the sequences of the features are used as the input vectors of the Hidden Markov Model (HMM) based recognizer. Since HLAC features are inherently shift-invariant and computationally inexpensive, the proposed method becomes robust to changes in the person's position and makes real-time gesture recognition possible. Experimental results of gesture recognition are shown to evaluate the performance of the proposed method.

In recent computer systems, a large portion of energy is consumed by on-chip cache accesses and data movement between cache and off-chip main memory. Reducing these memory system energy is indispensable for future microprocessors because power and thermal issues certainly become a key factor of limiting processor performance. In this paper, we discuss and evaluate how our architecture called SCIMA contributes to energy saving. SCIMA integrates software-controllable memory (SCM) into processor chip. SCIMA can save total memory system energy by using SCM under the support of compiler. The evaluation results reveal that SCIMA can reduce 5-50% of memory system energy and still faster than conventional cache based architecture.

In the last three decades of the 20th Century, research in speech recognition has been intensively carried out worldwide, spurred on by advances in signal processing, algorithms, architectures, and hardware. Recognition systems have been developed for a wide variety of applications, ranging from small vocabulary keyword recognition over dial-up telephone lines, to medium size vocabulary voice interactive command and control systems for business automation, to large vocabulary speech dictation, spontaneous speech understanding, and limited-domain speech translation. Although we have witnessed many new technological promises, we have also encountered a number of practical limitations that hinder a widespread deployment of applications and services. On one hand, fast progress was observed in statistical speech and language modeling. On the other hand only spotty successes have been reported in applying knowledge sources in acoustics, speech and language science to improving speech recognition performance and robustness to adverse conditions. In this paper we review some key advances in several areas of speech recognition. A bottom-up detection framework is also proposed to facilitate worldwide research collaboration for incorporating technology advances in both statistical modeling and knowledge integration into going beyond the current speech recognition limitations and benefiting the society in the 21st century.

In this letter we propose a new fast matching algorithm that has no degradation of predicted images such as found in the conventional full search (FS) algorithm, so as to reduce the amount of computation of the FS algorithm for motion estimation in real-time video coding applications. That is, our proposing algorithm reduces only unnecessary computations in the process of motion estimation without decreasing the prediction quality compared to the conventional FS algorithm. The computational reduction comes from rapid elimination of impossible motion vectors. In comparison to the FS algorithm, we obtained faster elimination of inappropriate candidate motion vectors using efficient matching units based on image complexity. Experimentally, we demonstrated that the unnecessary computations were removed by about 30% as compared to the other fast FS algorithms.

A fast nearest neighbor codeword search algorithm for vector quantization (VQ) is introduced. The algorithm uses three significant features of a vector, that is, the mean, the variance and the norm, to reduce the search space. It saves a great deal of computational time while introducing no more memory units than the equal-average equal-variance codeword search algorithm. With two extra elimination criteria based on the mean and the variance, the proposed algorithm is also more efficient than so-called norm-ordered search algorithm. Experimental results confirm the effectiveness of the proposed algorithm.

This paper presents a hardware-efficient architecture of tree-depth scan (TDS) and multiple quantization (MQ) scheme for zerotree coding in MPEG-4 still texture coder. The proposed TDS architecture can achieve its maximal throughput to area ratio and minimize the external memory access with only one wavelet-tree size on-chip buffer. The MQ scheme adopts the power-of-two (POT) quantization to realize a cost-effective hardware implementation. The prototyping chip has been implemented in TSMC 0.35 µm CMOS 1P4M technology. This architecture can handle 30 4-CIF (704576) frames per second with five spatial scalability and five SNR scalability layers at 100 MHz working frequency.

To increase the discriminating ability of the speech feature based on linear predictive coding (LPC) and increase its noise robustness, an SNR-dependent arcsin transform is applied to the autocorrelation sequence (ACS) of each analysis frame in a speech signal. Moreover, each component in the ACS is also weighted by the normalized reciprocal of the average magnitude difference function (AMDF) for emphasizing its peak structure. Experimental results for the task of Mandarin digit recognition indicate that the LPC speech feature employing the proposed scheme is more robust than some widely used LPC-based approaches over a wide range of SNR values.

The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexer-based architectural models with lower number of registers and buses, while presenting high throughput.

This paper presents a cell search scheme embedded with carrier frequency synchronization for inter-cell asynchronous orthogonal frequency-division multiplexing code-division multiplexing (OFDM-CDM) systems. Several subcarriers are dedicated to a differentially encoded synchronization channel (SCH). In the other subcarriers, data symbols and pilot symbols are two-dimensionally spread in the time-frequency domain. The cell search scheme consists of a three-stage cell search and a two-stage carrier-frequency synchronization, that is, coarse carrier-frequency acquisition, fast Fourier transform window-timing detection, SCH frame-timing detection, fine carrier-frequency synchronization, and cell-specific scrambling code (CSSC) identification. Simulation demonstrated that this scheme can identify the CSSC with high detection probability while precisely synchronizing the carrier frequency in severe frequency-selective fading channels.

This paper proposes a three-step cell search algorithm that utilizes only the common pilot channel (CPICH) in the forward link and employs spreading by a combination of a cell-specific scrambling code (CSSC) and an orthogonal short code for Orthogonal Frequency and Code Division Multiplexing (OFCDM) broadband packet wireless access. In the proposed cell search algorithm, the OFCDM symbol timing, i.e., Fast Fourier Transform (FFT) window timing, is estimated by detecting the guard interval timing in the first step. Then, in the second step, the frame timing and CSSC group are simultaneously detected by taking the correlation of the CPICH based on the property yielded by shifting the CSSC phase in the frequency domain. Finally, the CSSC within the group is identified in the third step. The most prominent feature of the proposed cell search algorithm is that it does not employ the conventional synchronization channel (SCH), which is exclusively used for the cell search. Computer simulation results elucidate that when the transmission power ratio of the CPICH to one code channel of the traffic channel (TCH) is 12 dB, the proposed cell search method achieves faster cell search time performance compared to the conventional method using the SCH with the transmission power ratio of the SCH to one code channel of the TCH of 6 dB. Furthermore, the results show that it can accomplish the cell search within 1.7 msec at 95% of the locations in a 12-path Rayleigh fading channel with the maximum Doppler frequency of 80 Hz and the r.m.s. delay spread of 0.32 µs.

A broadband RF front-end having a direct conversion architecture has been developed. The RF front-end consists of two broadband quadrature mixers, a multi-band local oscillator, and a broadband low-noise variable gain amplifier (LNVGA). The mixer achieves broadband characteristics through the incorporation of an in-phase power divider and a 45-degree power divider. The in-phase power divider achieves broadband characteristics through the addition of a compensation capacitor. The 45-degree power divider achieves broadband phase characteristics through the addition of a compensation capacitor and a compensation resistor. The local oscillator, which is composed of two VCOs, two frequency dividers, and four switches, can cover three systems including one FDD system. The LNVGA achieves its broadband characteristics without the use of reactance elements, such as inductors or capacitors. In a trial demonstration, when the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a demodulator experimentally demonstrated an amplitude balance of less than 1.6 dB and a quadrature phase error of less than 3 degrees. When the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a modulator demonstrated an image ratio of less than -30 dBc. The local oscillator demonstrated multi-band characteristics, which are able to cover the target frequencies for three systems (PDC, PHS, 2.4 GHz WLAN). From 900 MHz to 2.5 GHz, the amplifier shows a noise figure of less than 2.1 dB and a gain of 28 1.6 dB.

The motion estimation can choose the most suitable algorithm for different kinds of motion types, formats, and characteristics. The video encoding system can be optimized for quality, speed, and power consumption. In this paper, we propose a reconfigurable approach to a motion estimation algorithm and hardware architecture. The proposed algorithm determines motion type and then selects adapted block-matching algorithm for different kinds of motion sequences. The quality of our algorithm is better than that of the TSS and the BBGDS algorithm, or comparable to the performance of the better of the two, and the computational complexity of our algorithm is significantly less than that of the TSS. We also propose hardware architecture for realizing two kinds of motion estimations in the same hardware. We implemented the flexible and reconfigurable hardware architecture by using address generator unit, delay unit, and parameters and by using the hardware description language (VHDL) and the SYNOPSYS synthesis design tools. We analyze the performance of the algorithm and present adapted algorithm for a low cost real time application.