This paper describes a new reconfigurable processor architecture called REMARC (Reconfigurable Multimedia Array Coprocessor). REMARC is a small array processor that is tightly coupled to a main RISC processor. It consists of a global control unit and 64 16-bit processors called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decompression, and image processing. These applications typically use 8-bit or 16-bit data therefore, each nano processor has a 16-bit datapath that is much wider than those of other reconfigurable coprocessors. We have developed a programming environment for REMARC and several realistic application programs, DES encryption, MPEG-2 decoding, and MPEG-2 encoding. REMARC can implement various parallel algorithms which appear in these multimedia applications. For instance, REMARC can implement SIMD type instructions similar to multimedia instruction extensions for motion compensation of the MPEG-2 decoding. Furthermore, the highly pipelined algorithms, like systolic algorithms, which appear in motion estimation of the MPEG-2 encoding can also be implemented efficiently. REMARC achieves speedups ranging from a factor of 2.3 to 21.2 over the base processor which is a single issue processor or 2-issue superscalar processor. We also compare its performance with multimedia instruction extensions. Using more processing resources, REMARC can achieve higher performance than multimedia instruction extensions.

Thanks to rapid progress in computer technology and VLSI technology, we are approaching the stage where ordinary PCs will be able to handle real-time video signals as easily as they handle text data. First, features and applications of the video compression standard MPEG2 are surveyed as a typical video processing. It is clarified that real-time capability becomes more important as applications of MPEG2 widely spread. The trends of video coding in LSIs are summarized. And it is shown that the most advanced encoder/decoder LSI has an improved price-performance ratio that allows it to be adopted in consumer equipment. Finally, future directions of parallel architecture in video processing are surveyed in terms of special-purpose and general-purpose processing. The special approach has always taken the lead in video processing using sophisticated hardware-oriented parallel architectures. The general-purpose architecture method has gradually evolved in accordance with a software-oriented architecture. Both approaches will continue to evolve into a new stage by selecting possible parallel architectures such as multimedia instruction sets and process-level parallelism, and applying them in compound use. The so-called super processor architecture will emerge in the near future and it will be an ideal method that can manage rapid increase in requirements of capability and applicability in video processing.

Wavelength division multiplex (WDM) photonic networks are expected as the key for the global communication infrastructure. Recent increase of communication demands require large-scale highly-dense WDM systems, which results in severe requirements for optical cross-connect systems, such as cross-talk specification. In this paper, we propose a new optical path cross-connect system (OPXC) using matrix-WDM scheme, which makes it possible to reduce cross-talk requirements of WDM filters and to construct OPXC in modular structures. The matrix-WDM scheme is a concept of two-layered optical paths, which provides wavelength group managements in the fiber dispersion equalization and EDFA gain equalization.

The authors observed the correlation between electromagnetic noise and trace of discharge on surface for various surface areas of Cu in opening copper (Cu)-carbon (C) electrodes. In the case of Cu (anode)-C (cathode), the duration of sporadic burst noise generated by discharge becomes longer when Cu surface area is increased, and trace of discharge (melting area) distribute widely on electrodes. Also the forms of the burst noise in the start of arc are classified, and the traces of discharge correspond to each forms. The forms of the burst noise depend on the pattern which the trace of discharge are formed. As these results, the authors showed the correlation between form of burst noise and trace of discharge on electrode surface.

In a DC 50 V/3.3 A circuit, the spatial distributions of the spectral intensities of breaking arcs near the cathode for silver contacts were measured on the contact surfaces of three different shapes: flat and spherical (1 mm radius and 2 mm radius) and the arc temperature and the metal-vapor quantity were calculated from the spectral intensities. The influence of the contact shape on the arc temperature and the metal-vapor quantity were also examined, as well as the arc tracks on the contact surfaces and the gain and loss of the contacts. Findings show the distributions of spectral intensities are non-symmetrical from the beginning to the extinction of the breaking arc for the flat contact: However, they are symmetrical in the latter half of the breaking in spite of the number of breaking arcs and the shape of contact surface for the spherical contact. The relationship between the area of the arc tracks on the cathode and the shape of contact surface is the same as the relationship between the existent areas of measured spectra and the shape of the contact surface. For the spherical contacts, the arc temperature and the metal-vapor quantity are affected a little by the radius of the curved of contact surface and the number of breaking arcs. However, the longer the arc duration, the higher the metal-vapor quantity is in the latter period of the breaking arc. For the flat contacts, the metal-vapor quantity is lower than those for the spherical contacts. The gain and loss of the contacts are less and the arc duration is shorter for the flat contact than for the spherical contact.

Much of the data we deal with every day is organized hierarchically: file systems, library classification schemes and yellow page categories are salient examples. Business data too, benefits from a hierarchical organization, and indeed the hierarchical data model was quite prevalent thirty years ago. Due to the recently increased importance of X. 500/LDAP directories, which are hierarchical, and the prevalence of aggregation hierarchies in datacubes, there is now renewed interest in the hierarchical organization of data. In this paper, we develop a framework for a modern hierarchical data model, substantially improved from the original version by taking advantage of the lessons learned in the relational database context. We argue that this new hierarchical data model has many benefits with respect to the ubiquitous flat relational data model.

High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macrocells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-µm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.

The distributions of a spectral intensity of the breaking arc between silver contacts in DC 45-66 V/2.5-5.0 A circuits have been measured using a high-speed color video. As a result, a cathode brightening spot, which has a high spectral intensity, exists near the cathode surface. The cathode brightening spot expands with the increase of the contact gap, but its length expands until about 18µm. When the contact gap spreads over about 180 µm, a dark positive column appears and grows between the cathode brightening spot and the anode surface. The higher the interrupted current is, the larger the diameter of the cathode brightening spot will be. The maximum diameter of cathode brightening spot is 500 µm under these experiments.

This paper proposes a new wireless multimedia communication system based on hierarchical modulation, which gives unequal transmission reliability corresponding to the sensitivity to the transmission errors. In order to achieve high quality multimedia communication in a band-limited and time-variant fading channel, the proposed scheme changes the modulation scheme according to the contents of information. Numerical analysis shows that the proposed system is an effective high-quality and high-speed multimedia transmission technique in fading channel.

We propose a programming language, Flage, for building software systems which dynamically adapt to changing local situations. In our language, we construct applications by agents; concurrent mobile objects with the metalevel architecture. Metalevel programming facilities realize a self-control of an agent's actions and an autonomous adaptation to changes. We also introduce another kind of program element called field. A field represents a local situation around agents. For example, one field represents a virtual place to get local information in a network environment and another represents a virtual place where agents do cooperative works. If an agent enters a field, it gets programs and shared information in the field. By moving field to field, an agent can change its program composition by itself and it adapts to changing local situations. In this paper, we describe the language specification of Flage, the implementation of the platform for Flage programming and show some program examples.

This paper presents a new binding algorithm for a retargetable compiler which can deal with diverse architectures of application specific embedded processors. The architectural diversity includes a "non-orthogonal" datapath configuration where all the registers are not equally accessible by all the functional units. Under this assumption, binding becomes a hard task because inadvertent assignment of an operation to a functional unit may rule out possible assignment of other operations due to unreachability among datapath resources. We propose a new BDD-based algorithm to solve this problem. While most of the conventional methods are based on the covering of expression trees obtained by decomposing DFGs, our algorithm works directly on the DFGs so as to avoid infeasible bindings. In the experiments, a feasible binding which satisfies the reachability is found or the deficiency of datapath is detected within a few seconds.

The mapping from a global routing to a feasible detailed routing in a number of 2D array routing structures has been shown to be an NP-complete problem. These routing structures include the Xilinx style routing architecture, as well as architectures with significantly higher switching flexibility. In response to this complexity, a different class of FPGA routing structures called Greedy Routing Architectures (GRAs) have been proposed. On GRAs, optimally routing each switch box, in a specified order, leads to an optimal chip routing. Because routing each switch box takes polynomial time, the mapping problem on GRAs can be solved in polynomial time. In particular, an H-tree GRA with W2+2W switches per switch box (SpSB) and a 2D array GRA with 4W2+2W SpSB have been proposed. In this paper, we improve on these results by introducing an H-tree GRA with W2/2+2W SpSB and a 2D array GRA with 3.5W2+2W SpSB. These new GRAs have the same desirable mapping properties of the previously described GRAs, but use fewer switches.

For transmission of video signals, it is important that the system allows a certain degree of flexibility in bit rate as well as quality, depending upon the requirements of media and channel conditions. In this paper, we discuss the hierarchical transmission of Huffman code using multi-code/multi-rate DS/SS system to realize flexible transmission. We first discuss and show that the structure of Huffman code tree directly expresses hierarchical structure, and that parallel transmission of Huffman code can achieve hierarchical transmission. By assigning different transmission data rate to the bits in each stratum, it is possible to transmit different amount of information from each stratum. Further, we show the quality of each of the stratum can easily controlled by an appropriate power distribution to each parallel transmission branch.

One-way sensing simple multihead finite automata with bounds on the number of times of use of sensing function in accepting computations are studied. It is shown that the languages accepted by one-way sensing simple multihead finite automata with constant sensing function bound satisfy the semilinear property, and that for one-way sensing simple multihead finite automata, m+1 times of the use of sensing function are better than m.

Loosely wound short-arm two-wire Archimedean spiral antennas are investigated. It is shown that good circularly polarized waves with axial ratio less than 2 dB are obtained when the outer circumference C of the spiral antenna is in the range of about 1. 3λ < C < 1. 5λ, where λ is the free-space wavelength. To improve the antenna characteristics further, spiral antennas combined with a parasitic loop are examined. It is clarified that the parasitic loop greatly contributes to the improvement of the axial ratio and power gain.

In this paper, we propose a new conference key distribution scheme and the supervision of a conference when users are in a level-based hierarchy. In a conference key distribution system, one message is transmitted to the participants from a chairman, a legitimate member can decrypt it and reveal the common session key. The proposed scheme can be implemented without using any tamper-proof hardware. For users in a level-based hierarchy, by applying the key distribution scheme, the higher priority users can derive the conference key and supervise the lower level users' communications. Further, the users in the same level who are not members of the conference or in lower levels can not expose the conference key. To break the common session key, a malicious user has to suffer from the difficulty of factorization and discrete logarithm problems.

Computational expensiveness of the training techniques, due to the extensiveness of the data set, is among the most important factors in machine learning and neural networks. Oversized data set may cause rank-deficiencies of Jacobean matrix which plays essential role in training techniques. Then the training becomes not only computationally expensive but also ineffective. In [1] the authors introduced the theoretical grounds for dynamic sample selection having a potential of eliminating rank-deficiencies. This study addresses the implementation issues of the dynamic sample selection based on the theoretical material presented in [1]. The authors propose a sample selection algorithm implementable into an arbitrary optimization technique. An ability of the algorithm to select a proper set of samples at each iteration of the training has been observed to be very beneficial as indicated by several experiments. Recently proposed approaches to sample selection work reasonably well if pattern-weight ratio is close to 1. Small improvements can be detected also at the values of the pattern-weight ratio equal to 2 or 3. The dynamic sample selection approach, presented in this article, can increase the convergence speed of first order optimization techniques, used for training MLP networks, even at the value of the pattern-weight ratio (E-FP) as high as 15 and possibly even more.

This paper proposes a new processor architecture for manipulating the protocols of digital signal transport systems. In order to offer various kinds of telecommunication services, flexibility as well as high performance is required of digital signal transport systems. To realize such systems, this architecture consists of a core CPU, memories, and dedicated application-specific hardware. Software on the core CPU offers flexibility, while the dedicated hardware provides performance. A computer simulation confirms the efficiency of the architecture.

Conventional approaches to neural network training do not consider possibility of selecting training samples dynamically during the learning phase. Neural network is simply presented with the complete training set at each iteration of the learning. The learning can then become very costly for large data sets. Huge redundancy of data samples may lead to the ill-conditioned training problem. Ill-conditioning during the training causes rank-deficiencies of error and Jacobean matrices, which results in slower convergence speed, or in the worst case, the failure of the algorithm to progress. Rank-deficiencies of essential matrices can be avoided by an appropriate selection of training exemplars at each iteration of training. This article presents underlying theoretical grounds for dynamic sample selection (DSS), that is mechanism enabling to select a subset of training set at each iteration. Theoretical material is first presented for general objective functions, and then for the objective functions satisfying the Lipschitz continuity condition. Furthermore, implementation specifics of DSS to first order line search techniques are theoretically described.

We propose an information integration architecture for a man-machine interface to construct a new agent-based Computer Supported Cooperative Work (CSCW) system. The system acts as a clerk in cooperative work giving users the advantage of using cooperative work space. The system allows users to do their work in the style of an ordinary meeting because spontaneous expressions of speech and gestures by users are detected by sensors so that they can be integrated with a task model at several levels to create suitable responses in a man-machine interface. As a result, users can dedicate themselves to mutually understand other meeting members with no awareness of direction to the CSCW system. In this paper, we describe the whole system and its information integration architecture for the man-machine interface including, the principle of functions, the current status of the system and future directions.