In this paper, we propose a scalable service networking architecture as a TINA-like environment for providing flexibly various mobility services. The proposed architecture provides an environment that enables the advent of service providers and rapidly introduces multimedia applications, considering networks scalability. For supporting customized mobility services, this architecture adopts a new service component, which we call Omnipresent Personal Environment Manager (OpeMgr). In order to support mobile users who move between heterogeneous networks, for instance, between the TINA-like environment and the Internet environment, we propose a structure of a gateway. In addition, the proposed architecture uses the fixed and mobile agent approaches for supporting the user's mobility, and we evaluated their performances with comparing those approaches.

Advanced scientific and engineering problems require massively parallel computing. Critical to the designand ultimately the performanceof such computing systems is the interconnection network binding the computing elements, just as is the cardiovascular network to the human body. This paper develops a new interconnection network, "Tori connected mESHes (TESH)," consisting of k-ary n-cube connection of supernodes that comprise meshes of lower level nodes. Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion (up to a million processors), and it appears to be well suited for 3-D VLSI implementation, for it requires far fewer number of vertical wires than almost all known multi-computer networks. Presented in the paper are the architecture of the new network, node addressing and message routing, 3-D VLSI/ULSI considerations, and application of the network to massively parallel computing. Specifically, we discuss the mapping on to the network of stack filtering, a hardware oriented technique for order statistic image filtering.

In this paper, a systematic method which synthesizes the datapath of Application Specific Instruction Processor (ASIP) is proposed. The behavioral description of application is written in instruction code defined on abstract machine. We introduce register transfer graph (RTG) to represent instructions and synthesis constraint tree to select the combinations of synthesis constraints to explore design space along area and performance axis. The high performance is achieved by scheduling micro-operations of instruction in out-of-order. The practical datapath is synthesized by considering connection geometry as well as the maximum utilization of hardware resources. To reduce connection cost, data transfer paths are minimized by replacing an inefficient data transfer path with its bypass route. The feasibility of the proposed synthesis method is verified with several experimental instruction sequences.

High-speed display of 3-D objects in virtual reality environments is one of the currently important subjects. Shape simplification is considered an efficient method. This paper presents a method of hierarchical cube-based segmentation for shape simplification and multiresolution model construction. The relations among shape simplification, resolution and visual distance are derived firstly. The first level model is generated from scattered range data by cube-base segmentation with the first level cube size. Multiresolution models are then generated by re-sampling polygonal patch vertices of each former level model with hierarchical cube-based segmentation structure. The results show that the algorithm is efficient for constructing multiresolution models of free-form shape 3-D objects from scattered range data and high compression ratio can be obtained with little noticeable difference during the visualization.

A digital neuro chip with proliferating neuron architecture is described. This chip simulates a neural network model called the adaptive segmentation of quantizer neuron architecture (ASQA). It has proliferating neurons, and can automatically form the optimum network structure for recognition according to the input data. To develop inexpensive commercial hardware and implement a proliferating neuron architecture, we adopt a virtual neuron system for hardware implementation. Namely, this chip is implemented with only an arithmetic unit for network computations, and the network information such as network structure, synaptic weights and so on, are stored in external memories. We devise our original architecture which can efficiently memorize the network information, and moreover, construct a structured network using the ASQA model. As a result, we can recognize about 3,000 Kanji characters using a single chip and a recognition speed of 4.6 msec/character is achieved on a PC.

Genetic algorithms were introduced by Holland in 1975 as a method of solving difficult optimization problems by means of simulated evolution. A major drawback of genetic algorithms is their slowness when emulated by software on conventional computers. Described is an adaptation of the original genetic algorithm that is advantageous to hardware implementation along with the architecture of a hardware framework that performs the functions of population storage, selection, crossover, mutation, fitness evaluation, and survival determination. Programming of the framework is illustrated with the set coverage problem that exhibits a 6,000 speed-up over software emulation on a 100 MHz workstation.

Currently, a typical 5454 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea in the present paper is a power optimization for the data compressors based on a Window Detector. The role of the Window Detector is detecting the input data, activating a selected operation unit, choosing the optimized output data, and driving the next stage. It can reduce the power consumption drastically because only one selected operation unit (a Window) is activated. The power consumption of the proposed data compressors is reduced by about 33%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one. Furthermore, the power consumption dependent on the input data transition is shown for both the static CMOS logic and the nMOS pass transistor logic.

This paper proposes the Snow Crystal method, which aims to present the hierarchies of a large-scale telecommunication network on one screen. This will improve the user interface of a network operation system for network operations and management. With the proposed presentation method, locations of nodes are automatically set based on the number of hierarchy levels and the number of nodes. The nodes in the same hierarchy level are located on the same circle at even intervals. The center of the circle that corresponds to the top hierarchy level is set at the center of the screen. The radius of the circle is determined by the number of nodes. The centers of circles that correspond to the second hierarchy levels belonging to the nodes of the top hierarchy level, are located on a larger circle with the same center point as the top level circle at even intervals. The centers of circles that correspond to the third hierarchy levels are located at even intervals on a circle with the same center point as the second level circle, which the third levels belong to. The nodes of the subsequent levels are located in the same way. The proposed presentation method is successfully applied to a large-scale telecommunication network. Moreover, the results of an operating experiment with the proposed method show its effectiveness for presenting hierarchies of large-scale telecommunication networks.

In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.

This paper optimizes a hierarchical image transmission system based on the hierarchical modulation scheme in a band-limited Rayleigh fading channel. Authors analyze relations between hierarchical parameters and the image quality, and show that the existence of optimum hierarchical parameter that maximizes the received image quality.

This paper presents intelligent memory, a new memory architecture capable of providing efficient lock-free synchronization. In the intelligent memory, a sequence of operations on a shared object associated with that memory module can be processed without any intervention so that an environment for the synchronization can be provided by executing a critical section itself in that memory module. For this, we present a memory architecture for the intelligent memory having minimal instruction set and develop a progtramming model, called Critical Section Procedure (CSP), which consists of shared data structures and operations on them. Intelligent memory is intended to eliminate waste of processing time such as busy waiting in spin lock and the retry due to process contentions in existing lock-free synchronization schemes. Simulation results show that the intelligent memory provides better throughput compared with the spin lock and the existing lock-free synchronization schemes.

The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64 Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.

In this paper, we investigate inverse problems of the interval query problem in application to data mining. Let I be the set of all intervals on U = {1, 2, , n}. Consider an objective function f(I), conditional functions ui(I) on I, and define an optimization problem of finding the interval I maximizing f(I) subject to ui(I) > Ki for given real numbers Ki (i = 1, 2, , h). We propose efficient alogorithms to solve the above optimization problem if the objective function is either additive or quotient, and the conditional functions are additive, where a function f is additive if f(I) = ΣiIf^(i) extending a function f^ on U, and quotient if it is represented as a quotient of two additive functions. We use computational-geometric methods such as convex hull, range searching, and multidimensional divide-and-conquer.

Highly parallel scalable multiprocessing systems (HMPs) are powerful tools for solving large-scale scientific and engineering problems. However, these machines are difficult to program since algorithms must exploit locality in order to achieve high performance. Vienna Fortran was the first fully specified data-parallel language for HMPs that provided features for the specification of data distribution and alignment at a high level of abstraction. In this paper we outline the major elements of Vienna Fortran and compare it to High Performance Fortran (HPF), a de-facto standard in this area. A significant weakness of HPF is its lack of support for many advanced applications, which require irregular data distributions and dynamic load balancing. We introduce HPF +, an extension of HPF based on Vienna Fortran, that provides the required functionality.

In this paper we propose a new method for parallel execution of Prolog programs and present its implementation on a distributed memory parallel computer, Fujitsu AP1000. In our method a number of processes (named Prolog engines) explore different branches of a search tree (named tasks) in parallel, which is the same as OR-parallelism. Unlike OR-parallelism, the mapping between Prolog engines and tasks is statically determined like data parallelism. Each Prolog engine can decide which task is executed by the engine without communicating with the other engines. In many search problems, however, such static task mapping may cause imbalance on the processing time of each engine since the computational costs to explore branches may vary substantially. To cope with this issue, we devise a method to adjust the task imbalance by periodical exchanging how many tasks were processed for each engine. Also for reducing communication overhead in load balancing, we limit the scope of engines that exchange the load information each other. The effectiveness of our method is evaluated by measuring execution times for N Queens and the Traveling Salesman Problem on the AP1000. Using 512 processors, we obtained 355-fold speedup for N Queens and 343-fold speedup on the Traveling Salesman Problem.

In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array processors using systematic approach. The systematic approach guarantees to find optimal systolic array processors from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. The optimal systolic array processors are scalable, modular and suitable for VLSI implementation. An application of the designed systolic array processors to the prime-factor DFT is also presented.

This paper studies stabilization of timed discrete event systems with forcible events. We present an algorithm for computing the region of weak attraction for legal states.

In this paper we describe the implementation of complex architectures using a general design approach for two-phase asynchronous systems. This fundamental approach, called Event Controlled Systems, can be used to widely extend the utility of two phase systems. We describe solutions that we have developed that dramatically improve the performance of static and dynamic-logic asynchronous pipelines, and briefly describe a complex microprocessor designed using ECS.

In the proposed architecture, switching system hardware resources are allocated at the equipment level rather than at the component level of LSI chips. Equipment using these resources can thus be shared between independent systems. The efficiency of system development is improved by using structural elements called functional blocks (FBs). The hardware in each FB consists of a shared part (amicroprocessor, its peripheral circuitry, and memory) and a dedicated part that implements the specific functions of the FB. Firmware loaded into the microprocessor consists of a shared part and a dedicated part that corresponds to the hardware parts. Each FB also has its own built-in autonomous testing function to test the reliability of that FB and has its own identification function. By combining these FBs, this approach can flexibly cope with various switching system configurations for plain old telephone service (POTS), integrated services digital network (ISDN), and broad-band ISDN (B-ISDN). Tests using several types of FBs showed that the shared hardware and firmware parts of an FB can be shared between blocks. An architecture based on FBs results in a platform that can handle the hardware for various systems, making it easy to construct new switching systems.

We propose a new network architecture nemed Holonic Network for personalized multimedia communications, which is characterized by distributed cooperative networking based on autonomous management and all-optical transport networks. We than propose autonomous routing method. Moreover, an information searching method and a route generation method with network maps, which are essential for this network, are proposed. Lastly, we evaluate the proposed network performance by theoretical analysis and system emulation.