This paper presents a case study of synthesis of the industrial embedded microcontroller HT48100 and analysis of performance, cost and software compatibility for its implementation alternatives, using the hardware/software co-design system for microcontrollers/microprocessors PIPER-II. The synthesis tool accepts as input the instruction set architecture (behavioral) specification, and produces as outputs the pipelined RTL designs with their simulators, and the reordering constraints which guide the compiler backend to optimize the code for the synthesized designs. A compiler backend is provided to optimize the application software according to the reordering constraints. The study shows that the co-design approach was able to help the original design team to analyze the architectural properties, identify inefficient architecture features, and explore possible architectural improvements and their impacts in both hardware and software. Feasible future upgrades for the microcontroller family have been identified by the study.

Parallelization of the P-complete problem is known to be difficult. In this paper, we consider the parallelizability of a stack breadth-first search (stack BFS) problem, which is proved to be P-complete. We first propose the longest path length (LPL) as a measure for the P-completeness of the stack BFS. Next, using this measure, we propose an efficient parallel algorithm for the stack BFS. Assuming the size and LPL of an input graph are n and l, respectively, the complexity of the algorithm indicates that the stack BFS is in the class NCk+1 if l = O(logk n), where k is a positive integer. In addition, the algorithm is cost optimal if l=O(nε), where 0 < ε < 1.

Distributed Denial of Service (DDoS) attacks are a pressing problem on the Internet as demonstrated by recent attacks on major e-commerce servers and ISPs. Since the attack is highly distributed, an effective solution must be formulated with a distributed approach. Recently, some solutions, in which intermediate network nodes filter or shape congested traffic, have been proposed. These solutions may decrease the congested traffic, but they still cause "collateral victims problem," that is, legitimate packets may be discarded mistakenly. In this paper, we propose Active Countermeasure Platform to minimize traffic congestion and to address the collateral victim problem using the Active Networks paradigm, which incorporates programmability into intermediate network nodes. Our platform can prevent overloading of the target and consuming the network bandwidth of both the backbone and the protected site autonomously. In addition, it can improve the collateral victim problem based on user policy. This paper shows the concept of our platform, system design and evaluation of the effectiveness using a prototype.

This paper proposes a three-step cell search algorithm utilizing a synchronization channel (SCH) and common pilot channel (CPICH) in the forward link for OFCDM (Orthogonal Frequency and Code Division Multiplexing) broadband packet wireless access, and evaluates the cell search time performance by computer simulation. In the proposed three-step cell search algorithm, the OFCDM symbol timing, i.e., Fast Fourier Transform (FFT) window timing is estimated employing SCH or guard interval (GI) correlation in the first step. Then, the frame timing is detected by employing the SCH and the cell-specific scrambling code (CSSC) is identified by the CPICH in the second and third steps, respectively. Computer simulation results elucidate that the proposed three-step cell search algorithm achieves fast cell search time performance, i.e., cell detection probability of 90% within approximately 50 msec, assuming the number of CSSCs of 512 in a 19 hexagonal-cell model. We also clarify that there is no prominent difference in cell search time performance between the two employed SCH structures, time-multiplexed and frequency-multiplexed, assuming that the total transmit power of the SCH is the same. Based on the comparison of four substantial cell search algorithms, the GI-plus-SCH correlation method, in which FFT windowing timing detection, frame timing detection, and CSSC identification are performed by GI correlation, frequency-multiplexed SCH, and CPICH, respectively, exhibits the cell search time of approximately 44 msec at the detection probability of 90% with an optimized averaging parameter in each step.

The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of 1-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.

This paper devises a sophisticated approach to the performance estimation of an embedded hardware-software codesign system at the architecture level, which intends to optimize the hardware-software configuration in terms of processing time, power dissipation, and hardware cost. A distinctive feature of this approach consists in constructing a performance estimation model proper to each component of an embedded system, such as CPU core, RAM/ROM, cache memory, and application-specific hardware, by taking account of not only the functional performance but also the data transfer. The proposed estimation schemes are incorporated into an existing instruction set simulator, so that the actual performance can be estimated accurately at the architecture level. The experimental results demonstrate that the performance estimation approach enables the precise design decision at the architecture level, which greatly contributes toward enhancing the design ability dedicatedly for mobile appliances.

A broadband RF front-end having a direct conversion architecture has been developed. The RF front-end consists of two broadband quadrature mixers, a multi-band local oscillator, and a broadband low-noise variable gain amplifier (LNVGA). The mixer achieves broadband characteristics through the incorporation of an in-phase power divider and a 45-degree power divider. The in-phase power divider achieves broadband characteristics through the addition of a compensation capacitor. The 45-degree power divider achieves broadband phase characteristics through the addition of a compensation capacitor and a compensation resistor. The local oscillator, which is composed of two VCOs, two frequency dividers, and four switches, can cover three systems including one FDD system. The LNVGA achieves its broadband characteristics without the use of reactance elements, such as inductors or capacitors. In a trial demonstration, when the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a demodulator experimentally demonstrated an amplitude balance of less than 1.6 dB and a quadrature phase error of less than 3 degrees. When the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a modulator demonstrated an image ratio of less than -30 dBc. The local oscillator demonstrated multi-band characteristics, which are able to cover the target frequencies for three systems (PDC, PHS, 2.4 GHz WLAN). From 900 MHz to 2.5 GHz, the amplifier shows a noise figure of less than 2.1 dB and a gain of 28 1.6 dB.

The motion estimation can choose the most suitable algorithm for different kinds of motion types, formats, and characteristics. The video encoding system can be optimized for quality, speed, and power consumption. In this paper, we propose a reconfigurable approach to a motion estimation algorithm and hardware architecture. The proposed algorithm determines motion type and then selects adapted block-matching algorithm for different kinds of motion sequences. The quality of our algorithm is better than that of the TSS and the BBGDS algorithm, or comparable to the performance of the better of the two, and the computational complexity of our algorithm is significantly less than that of the TSS. We also propose hardware architecture for realizing two kinds of motion estimations in the same hardware. We implemented the flexible and reconfigurable hardware architecture by using address generator unit, delay unit, and parameters and by using the hardware description language (VHDL) and the SYNOPSYS synthesis design tools. We analyze the performance of the algorithm and present adapted algorithm for a low cost real time application.

Finding corresponding edges is considered being the most difficult part of edge-based stereo matching algorithms. Usually, correspondence for a feature point in the first image is obtained by searching in a predefined region of the second image, based on epipolar line and maximum disparity. Reduction of search region can increase performances of the matching process, in the context of execution time and accuracy. Traditionally, hierarchical multiresolution techniques, as the fastest methods are used to decrease the search space and therefore increase the processing speed. Considering maximum of directional derivative of disparity in real scenes, we formulated some relations between maximum search space in the second images with respect to relative displacement of connected edges (as the feature points), in successive scan lines of the first images. Then we proposed a new matching strategy to reduce the search space for edge-based stereo matching algorithms. Afterward, we developed some fast stereo matching algorithms based on the proposed matching strategy and the hierarchical multiresolution techniques. The proposed algorithms have two stages: feature extraction and feature matching. We applied these new algorithms on some stereo images and compared their results with those of some hierarchical multiresolution ones. The execution times of our proposed methods are decreased between 30% to 55%, in the feature matching stage. Moreover, the execution time of the overall algorithms (including the feature extraction and the feature matching) is decreased between 15% to 40% in real scenes. Meanwhile in some cases, the accuracy is increased too. Theoretical investigation and experimental results show that our algorithms have a very good performance with real complex scenes, therefore these new algorithms are very suitable for fast edge-based stereo applications in real scenes like robotic applications.

In this paper, we present a new soft-decision iterative decoding algorithm using an efficient minimum distance search (MDS) algorithm. The proposed MDS algorithm is a top-down and recursive MDS algorithm, which finds a most likely codeword among the codewords at the minimum distance of the code from a given codeword. A search is made in each divided section by a "call by need" from the upper section. As a consequence, the search space and computational complexity are reduced significantly. The simulation results show that the proposed decoding algorithm achieves near error performance to the maximum likelihood decoding for any RM code of length 128 and suboptimal for the (256, 37), (256, 93) and (256, 163) RM codes.

Positioning service is indispensable in next-generation mobile communications and is expected to have various applications. This paper proposes a positioning method using first path searching in the correlation between a received signal and the replica of the transmitted signal to calculate the TDoA (Time Difference of Arrival) and ToA (Time of Arrival) for W-CDMA (Wideband-Code Division Multiple Access) and OFDM (Orthogonal Frequency Division Multiplexing) in a broadband cellular mobile communication systems. W-CDMA and OFDM are both powerful modulation candidates in the next generation and are compared here in terms of positioning accuracy. The chip correlation in W-CDMA and the total signal correlation in OFDM are used. Uplink and downlink type positioning methods are also compared. Computer simulation shows that the proposed method gives good positioning performance in multi-path fading channels.

Hierarchical Mobile IPv6 (HMIPv6) has been proposed to accommodate frequent mobility of terminals within the Internet. It utilizes a router, named Mobility Anchor Point (MAP), so that networks can manage mobile terminals without floods of signaling message. Note here that, particularly in a wide area network, such as a mobile communication network, it is efficient to distribute several MAPs within the same network and make the MAP domains cover overlapped areas. This enables the network to manage the terminals in a flexible manner according to their different mobility scenarios. The method described in the Internet-Draft at the IETF, however, lets mobile terminals select its MAP. This may cause load concentration at some particular MAPs and/or floods of signaling messages, because the terminals may not select a feasible MAP in a desirable manner. In this paper, a MAP selection method in distributed-MAPs environment is proposed. It reduces signaling messages to/from outside networks without load concentration at any particular MAPs. Finally, we show that the proposed method works effectively by simulation experiments.

When we want to know if it is a win or a loss at a given position of a game (e.g. chess endgame), the process to figure out this problem corresponds to searching an AND/OR tree. AND/OR-tree search is a method for getting a proof solution (win) or a disproof solution (loss) for such a problem. AO* is well-known as a representative algorithm for searching a proof solution in an AND/OR tree. AO* uses only the idea of proof number. Besides, Allis developed pn-search which uses the idea of proof number and disproof number. Both of them are best-first algorithms. There was no efficient depth-first algorithm using (dis)proof number, until Seo developed his originative algorithm which uses only proof number. Besides, Nagai recently developed PDS which is a depth-first algorithm using both proof number and disproof number. In this paper, we give a proof for the equivalence between AO* which is a best-first algorithm and Seo's depth-first algorithm in the meaning of expanding a certain kind of node. Furthermore, we give a proof for the equivalence between pn-search which is a best-first algorithm and df-pn which is a depth-first algorithm we propose in this paper.

This paper presents a new Reinforcement Learning (RL) method, called "Labeling Q-learning (LQ-learning)," to solve the partially obervable Markov Decision Process (POMDP) problems. Recently, hierarchical RL methods are widely studied. However, they have the drawback that the learning time and memory are exhausted only for keeping the hierarchical structure, though they wouldn't be necessary. On the other hand, our LQ-learning has no hierarchical structure, but adopts a new type of internal memory mechanism. Namely, in the LQ-learning, the agent percepts the current state by pair of observation and its label, and then, the agent can distinguish states, which look as same, but obviously different, more exactly. So to speak, at each step t, we define a new type of perception of its environment õt=(ot,θt), where ot is conventional observation, and θt is the label attached to the observation ot. Then the classical RL-algorithm is used as if the pair (ot,θt) serves as a Markov state. This labeling is carried out by a Boolean variable, called "CHANGE," and a hash-like or mod function, called Labeling Function (LF). In order to demonstrate the efficiency of LQ-learning, we will apply it to "maze problems" in Grid-Worlds, used in many literatures as POMDP simulated environments. By using the LQ-learning, we can solve the maze problems without initial knowledge of environments.

Intensive accesses to a web server causes its response delay and/or service suspension. We propose, to solve the problem in this paper, a service model for web servers grounded upon admission control and call waiting service, which are common approaches to designing telephone systems. Software architecture which consists of a front-end server and child servers is also designed based on the service model. Through performance evaluation for an implementation of the architecture, it is shown that the overall throughput becomes much better by keeping child web servers from overload. We drew a conclusion that the architecture enhances flexibility of a resulting software with discussions from the extensibility view.

Both tiers are assumed to share the same frequency band. Unlike a single tier cell environment, interference components to be considered in a hierarchical cell environment include the inter-tier interference as well as the intra-cell and the inter-cell interference. The numerical results show that the transmission power ratio between the macro cell and the micro cell affects the forward link capacity. And the results also show that the macro cell capacity increases as the mobile moves toward the edge of the macro cell. Moreover, soft handoff makes it possible to obtain a higher forward link capacity in the handoff region.

This paper investigates the cell search time performance of our previously proposed three-step cell search method in a two-cell site environment by laboratory and field experiments supporting asynchronous cell site operation, which is one of the most notable features of wideband direct sequence code division multiple access (W-CDMA) mobile communications. The cell search methods used in the paper are based on the ongoing third generation partnership project (3GPP), in which our original scheme was refined with respect to several points in order to reduce the complexity of the receiver. The experimental results demonstrate that the method achieves the fast cell search time of less than one second in real multipath-fading channels. The cell search is accomplished in less than approximately 700 msec at 90% of the detection probability when 4.7% and 0.5% of the total transmit power of a cell site is assigned to the common pilot channel (CPICH) and synchronization channels (SCHs), respectively, in a two-cell site environment. We also elucidate that the cell search time at the detection probability of 90% using time switched transmit diversity (TSTD) is decreased by approximately 100 msec compared to that without TSTD in low-mobility environments such as the average vehicular speed of 5 km/h with a transmit power assignment of the CPICH of 4.7%.

In this letter a low-complexity and low-power realization of the 2D discrete-cosine-transform and its inverse (DCT/IDCT) is presented. A VLSI circuit based on the Chen algorithm with the distributed arithmetic approach is described. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the circuit power consumption. To this aim, input signal statistics have been extracted from H.263/MPEG verification models. Finally, circuit performance is compared to known software solutions and dedicated full-custom ones.

This paper discusses a new type of semi-supervised document clustering that uses partial supervision to partition a large set of documents. Most clustering methods organizes documents into groups based only on similarity measures. In this paper, we attempt to isolate more semantically coherent clusters by employing the domain-specific knowledge provided by a document analyst. By using external human knowledge to guide the clustering mechanism with some flexibility when creating the clusters, clustering efficiency can be considerably enhanced. Experimental results show that the use of only a little external knowledge can considerably enhance the quality of clustering results that satisfy users' constraint.

This paper describes a method for hands-free speech recognition, and particularly for the simultaneous recognition of multiple sound sources. The method is based on the 3-D Viterbi search, i.e., extended to the 3-D N-best search method enabling the recognition of multiple sound sources. The baseline system integrates two existing technologies--3-D Viterbi search and conventional N-best search--into a complete system. Previously, the first evaluation of the 3-D N-best search-based system showed that new ideas are necessary to develop a system for the simultaneous recognition of multiple sound sources. It found two factors that play important roles in the performance of the system, namely the different likelihood ranges of the sound sources and the direction-based separation of the hypotheses. In order to solve these problems, we implemented a likelihood normalization and a path distance-based clustering technique into the baseline 3-D N-best search-based system. The performance of our system was evaluated through experiments on simulated data for the case of two talkers. The experiments showed significant improvements by implementing the above two techniques. The best results were obtained by implementing the two techniques and using a microphone array composed of 32 channels. More specifically, the Word Accuracy for the two talkers was higher than 80% and the Simultaneous Word Accuracy (where both sources are correctly recognized simultaneously) was higher than 70%, which are very promising results.