The up and coming multimedia services are based on real-time high-speed networks. For efficient operation of such services, real-time and precise network management is essential. In this paper, we show that presently available MIB designs are severely inadequate to support real-time network management. We point out and analyze the management constraints and bottlenecks. The concept of quality of management of management information is introduced and its importance in practical network management is discussed. We have proposed a new MIB architecture that will raise the quality of management information to meet the requirements of managing high-speed networks and multimedia services. Experimental results from a prototype implementation of the new MIB architecture are presented.

In retrieving information from databases widely distributed in a network, the first thing to do is to search and find the database where the required information is stored. We call this the information searches rather than the retrievals. In this paper, we present a search and retrieval method for multimedia information, especially images. First, we formalize the general elements of information search and introduce a new search concept based on entropy reduction. Next, we discuss recent new technologies for image retrieval and introduce a new image retrieval system called VideoReality. Third, we present several methods of searching in the network- for example, the Internet robot TITAN, and a new search method for images distributed in the network that is based on the hierarchical structure of image retrieval. Finally, we discuss the network control and design concepts appropriate for information search and retrival.

Efficient parallel algorithms for several problems on proper circular arc graphs are presented in this paper. These problems include finding a maximum matching, partitioning into a minimum number of induced subgraphs each of which has a Hamiltonian cycle (path), partitioning into induced subgraphs each of which has a Hamiltonian cycle (path) with at least k vertices for a given k, and adding a minimum number of edges to make the graph contain a Hamiltonian cycle (path). It is shown here that the above problems can all be solved in logarithmic time with a linear number of EREW PRAM processors, or in constant time with a linear number of BSR processors. A more important part of this work is perhaps the extension of basic BSR to allow simultaneous multiple BROADCAST instructions.

In estimating the performances of Distributed control Dynamic Channel Assignment (DDCA) strategies in sector cell layout systems, we find that sector cell layout systems with DDCA achieved a large system capacity. Moreover, we also indicate the problem, which is the increase of occurrences of cochannel interference, raised by using DDCA in sector cell layout systems. The new channel assignment algorithm, which is called Channel Searching on Direction of Sector (CSDS), is proposed to cope with the problem. CSDS assigns nominal channels to each sector according to their direction so that the same frequency channel tends to be used in sectors having the same direction. We show, by simulations, that CSDS is an adequate algorithm for sector cell layout systems because it significantly improves performance on co-channel interference while only slightly decreasing system capacity.

In this paper, we propose an approach for railway scheduling based on iterative repair, a technique that starts with a complete but possibly flawed schedule and searches through the space of possible repairs. The search is guided by an earliest-conflict-first heuristic that attempts to repair the earliest constraint violation while minimizing the value of objective function. Since cycles may exist among a sequence of repairs during the repair process, a cycle detection and resolution scheme is proposed to prevent infinite loops. Experimental results show that the efficiency of the repair algorithm improves significantly when cycle detection is incorporated.

Ferroelectic nonvolatile technology comprises the ferroelectric material technology, the process technology and the circuit technology. Bi based layered Perovskyte ferroelectric material, SrBi2Ta2O9, so called "Y 1," has superior characteristics in terms of endurance and nonvolatile properties, which is confirmed by a 256kbit ferroelectric nonvolatile memory. Critical issues regarding the ferroelectric process are reviewed. The lT/lC cell configuration which is essential for a high density memory and the reference voltage generator employed in the 256 k memory are described as is the architecture to reduce the power consumption of the memory.

Full-search block-matching motion estimation is a popular method to reduce temporal redundancies in video sequence. Due to its excessive computational load, parallel processing architectures are often required for real-time processing. One of the architectures is Hsieh's architecture based on systolic array processor and shift register arrays. Serial input characteristic of his scheme can reduce the number of pixel inputs to one, at the expense of significantly increasing the initialization time. This paper presents a modified and generalized Hsieh's architecture to reduce the initialization time. The proposed architecture can easily control data flows by rearranging shift register arrays and input-pin counts by using multiplexers on input stage, while retaining good properties of Hsieh's. The proposed architecture has the following advantages: (1) it allows controllable data inputs to save the pin counts, (2) it is flexible to the dimensional change of the search area via simple control, (3) it can operate in real time for video conference applications, and (4) it has simple and modular structure which is quite suitable for VLSI implementation. For verification of the proposed architecture, VHDL simulations are performed and some results are given.

A crossing charge recycle refresh(CCRR) scheme and a serial charge recycle refresh(SCRR) scheme are proposed for the large capacity DRAMs with hierarchical bit-line architecture to reduce main bit-line charging current. A separated driver sense-amplifier(SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplifiers. These circuits are applied to an experimental 1-Gb DRAM, which achieves reduction of main bit-line charging current to 37.5%.

A structural active-object system (SAOS) is a transition-based object-oriented system suitable for rapid development of hardware logic simulators. A SAOS consists of a collection of interacting structural active objects (SAOs), whose behaviors are determined by the transition statements provided in their class definitions. Furthermore, SAOs can be structurally and hierarchically composed from their component SAOs like hardware components. These features allow SAOs to model components for circuit simulation more naturally than passive objects used in ordinary object-oriented programming. Also, we can easily create new kinds of components by using the inheritance mechanism. Executions of transition statements may be event-and/or time-driven, and hence digital, analog, and mixed-mode simulation is possible. Prototype simulation programs with graphical user interfaces have been developed as SAOS programs for digital, analog, and mixed-mode circuit simulation.

This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.

We propose an architecture of a high-speed internetworking device using central control method. Co-operations of hardware and software is required to realize high relay performance. For the hardware, we have designed an original bus arbitration control method to achieve a high throughput of a data bus. For the software, we have devided a normal relay processing from other processing and built it as a basic function of the monitor. By this method, relay perfomance improves dramatically, because of a multiple effect of the reduction of software overheads and the improvement of cache hit ratio. We have developed the prototype device and confirmed the effects of the proposed method.

This paper presents a parallel move generation of a Chess machine system for achieving the purpose of reducing the number of move generation cycles. The parallel system is composed of five move generation modules which share the move generating cycles to reduce the time of building a game tree. Simulation results show that the proposed parallel move generation architecture takes about half of the number of move generation cycles to build a game tree that is the same as the one built by a sequential move generation module.

A tree embedded in a plane can be characterized as an unrooted and cyclically ordered tree (CO-tree). This paper describes new definitions of three distances between CO-trees and their computing methods. The proposed distances are based on the Tai Mapping, the structure preserving mapping and the strongly structure preserving mapping, respectively, and are called the Tai distance (TD), the structure preserving distance (SPD) and the strongly structure preserving distance (SSPD), respectively. The definitions of distances and their computing methods are simpler than those of the old definitions and computing methods, respectively. TD and SPD by the new definitions are more sensitive than those by the old ones, and SSPDs by both definitions are equivalent. The time complexities of computing TD, SPD and SSPD between CO-trees Ta and Tb are OT (N2aN2a), OT(maNaN2b) and OT(mambNaNb), respectively, where Na(Nb) and ma(mb) are the number of vertices in tree Ta(Tb)and the maximum degree of a vertex in Ta(Tb), respectively. The space complexities of these methods are OS(NaNb).

This paper describes the characteristics of the radiated magnetic field caused by breaking arcs between a pair of Ag, AgDdO, AgSnO2 or Pd contacts in a DC 50V/1.9-5.0A circuit. For Ag contacts, in an interrupting current less than 3.3A, the radiated magnetic field appears strongly during the metallic phase arc where the smaller the interrupting current is, the more the number of frequency spectra of the radiated magnetic field becomes. In an interrupting current more than 3.3A, the radiated magnetic field appears weakly during the metallic-gaseous transition period. For AgSnO2 and AgCdO contacts, there is a weak radiated magnetic field in the metallic-gaseous transition period and the smaller the interrupting current is, the stronger the maximum intensities of frequency spectra of the radiated magnetic field in the transition period are. For Pd contacts, the maximum intensities of frequency spectra of the radiated magnetic field do not change very much from the beginning to the end of the breaking arc, which do not depend on the interrupting current. From the experimental results, the maximum intensities of frequency spectra of the radiated magnetic fields are found to depend on the contact material. And their distribution depends on the impedance of the circuit containing the contacts that generates the breaking arc.

Arc discharge at switching contacts is one of the key phenomena, because it strongly affects material wear/transfer, contact resistance and electromagnetic interference (EMI). The arc discharge is classified into various types from the viewpoint of its sustaining mechanism and voltage waveform. They are mainly steady arc, showering arc and initial arc. Furthermore, a steady arc consists of two stages named metallic phase arc and gaseous phase arc. In the metallic, phase arc, metal ious from the electrodes mainly sustain the arc. On the other hand, gas ions from the surrounding atmosphere play an important role in the gaseous phase. Each phase arc has different influence on contact performance and EMI. The purpose of this paper is to review the arc discharges at light duty electrical contacts, and to survey the effects of arc discharges on material transfer and EMI.

Induced noises from breaking contact arc discharge and sliding contact discharge of dc motor are measured by pick up coil and current probe. Statistical properties, amplitude distribution probability (APD), of induced noise waveform are analyzed by simple method using intermediate frequency of spectrum analyzer. It is shown that APD characteristics can be used to estimate statistical characteristics and peak value of induced noise. Simulation model of the noise made by the combination of Gaussian noise is mentioned. The model called the composite noise generator (CNG) can be good fit to the real characteristics of both noises from breaking arc and dc motor. Applications of the CNG for noise filter using toroidal coil shows that the CNG is useful to realize the test of noise suppression characteristics. What parameters of the CNG should be considered is described for further applications.

Among three factors mainly affecting the cache access time, i. e., hit access time, miss rate and miss penalty, previous approaches were focused on reducing the hit access time and miss rate. In this paper, we propose a scheme called MPC (Miss-Predicting Cache) which achives additional reduction of the average instruction cache access time through reducing the miss penalty. The MPC scheme which predicts cache miss and starts cache miss operations in advance, therefore, is supplementary to previous cache schemes targeted for reducing the miss rate and/or hit access time. Performance of the MPC scheme was evaluated using dinero, a trace-driven cache simulator, with the estimation of silicon area using 0.8 µm CMOS standard cell library.

This letter proposes evolutionary digital filters (EDFs) as new adaptive digital filters. The EDF is an adaptive filter which is controlled by adaptive algorithm based on the evolutionary strategies of living things. It consists of many linear/time-variant inner digital filters which correspond to individuals. The adaptive algorithm of the EDF controls and changes the coefficients of inner filters using the cloning method (the asexual reproduction method) or the mating method (the sexual reproduction method). Thus, the search algorithm of the EDF is a non-gradient and multi-point search algorithm. Numerical examples are given to show the effectiveness and features of the EDF such that they are not susceptible to local minimum in the multiple-peak performance surface.

This article analyzes dynamics of the chaotic neural network and minimum searching principle of this network. First it is indicated that the dynamics of the chaotic newral network is described like a gradient decent, and the chaotic neural network can roughly find out a local minimum point of a quadratic function using its attractor. Secondly It is guaranteed that the vertex corresponding a local minimum point derived from the chaotic neural network has a lower value of the objective function. Then it is confirmed that the chaotic neural network can escape an invalid local minimum and find out a reasonable one.

Many ATM switching modules with high performance have been proposed and analyzed. A development of a large scale ATM switching system (e.g., used as a central switch) is the key to realization of the broadband ISDN. However, the dimension of ATM switching ICs is limited by the technological and physical constraints on VLSI. A multistage switching configuration is one of the promising configurations for a large scale ATM switch. In this paper, we treat a 3-stage switching configuration with no internal bufferes; i.e., bufferless switches are employed at the first and second stages, and output buffered switches at the third stage. A short-term cell loss probability is analyzed in order to examine the influence of bursty traffic on performance of the bufferless switch used at the first two stages. Furthermore, we propose a 4-stage switching configuration with traffic distributors added at the first stage. This switch provides more paths between a pair of input and output ports than the 3-stage switching configuration mentioned above. A few schemes to distribute cells are compared. It is shown that the distributor successfully reduces the deterioration of cell loss probability due to bursty traffic by splitting incoming cells into several switching modules.