In recent years, and increasing number of studies have been reported regarding multimedia LANs that integrate voice, data and video communications. The Movable Boundary method has been suggested as a way to integrate circuit and packet switching. However, how this can be practically managed, especially for multimedia LANs, is not clear. Working under the assumption that an optical loop network in used as a multimedia LAN, we propose Hybrid Allocation as a new Movable Boundary method. Hybrid Allocation features traffic prediction for circuit switching calls, and timeslot allocation close to the boundary of circuit and packet switching areas. Evaluations of traffic simulation and network efficiency show it to be a promising architecture for integrating circuit and packet switching on a multimedia LAN.

The storage utilizations of existing similar key search files based on B+-tree and extensible hashing were under 70% and should be improved. A similar key search file based on extensible hashing with partial expansion and that on linear hashing with partial expansion are proposed. Computer simulations on about 230 thousand English words show that the storage utilizations of the files with 32 expansive steps are about 97%.

The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.

In this paper we discuss the limiting behavior of the search direction of the steepest descent method in minimizing the Rayleigh quotient. This minimization problem is equivalent to finding the smallest eigenvalue of a matrix. It is shown that the search direction asymptotically alternates between two directions represented by linear combinations of two eigenvectors of the matrix. This is similar to the phenomenon in minimizing the quadratic form. We also show that these eigenvectors correspond to the largest and second-smallest eigenvalues, unlike in the case of the quadratic form.

This letter shows an architectural approach for analyzing real-time aspects of distributed multimedia processing systems. The results of this letter are 1) to propose the concept real-time supporting environments which consist of real-time traffic management/control environment and real-time application environment and 2) to analyze the real-time requirements of such environments.

This paper proposes a novel VLSI architecture capable of processing the Lempel-Ziv-based data compression algorithm very fast. The architecture is composed of five main blocks, i.e., a PE-based Match Block, a Consecutive Hit Checker, a Pointer Generator, a Length Generator, and a Code Packer. Flexibility of the PE-based structure makes it possible to adapt to various buffer sizes without any loss of speed or additional control overhead. Since it is designed as a VLSI-oriented architecture, it has simple control logic circuitry. It processes exactly one character per clock cycle and the update of a dictionary buffer is automatically done, therefore it does not require additional accumulated shift operations to prepare for the dictionary buffer. The shift operations have been major problems commonly found in most other architectures. When implemented with the currently available 0.5µm CMOS technology, it is proven by critical path analysis that the architecture can achieve over 100 mega samples (characters) per second with a clock frequency of 100 MHz. This is fast enough for real time data compression for many applications.

A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.

In [2] Ibarra introduced a restricted version of one-way multihead pushdown automaton (PDA), called a simple one-way multihead PDA, and showed that such machines recognize only languages with semilinear property. The main result of this paper is that for each k 1, simple (sensing) one-way (k + 1)-head PDA's are more powerful than simple (sensing) one-way k-head PDA's. This paper also investigates closure properties for simple (sensing) one-way multihead PDA's

Let SeH{0}(k) [NSeH{0}(k)] denote the class of languages over a one-letter alphabet accepted by two-way sensing deterministic [nondeterministic] k-head finite automata. This paper shows that (i) SeH{0}(2)SeH{0}(3), and (ii) NSeH{0}(2) NSeH{0}(3). This gives an affirmative answer to an open problem in Ref. [3].

This paper describes a new region segmentation method which is detectable carcinoma regions from hematoxylin and eosin (HE)-stained breast tumor images using collective behaviors of artificial organisms. In this model, the movement characteristics of artificial organisms are controlled by the gene, and the adaptive behavior of artificial organisms in the environment, carcinoma regions or not, is evaluated by the texture features.

Analog computation is a processing method that solves problems utilizing an analogy of a physical system to the problem. As it is based on actual physical effects and not on symbolic operations, it is therefore a promising architecture for quantum processors. This paper presents an idea for relating quantum structures with analog computation. As an instance, a method is proposed for solving an NP-complete (nondeterminis-tic polynomial time complete) problem, the three-color-map problem, by using a quantum-cell circuit. The computing process is parallel and instantaneous, so making it possible to obtain the solution in a short time regardless of the size of the problem.

For very low bit-rate video coding such as under 64 kbps, it is unreasonable to encode and transmit all the information. Thus, it is very important to choose the "important" information and encode it efficiently. In this paper, we first propose an image separation-composition method to solve this problem. At the encoder, an image is separated into a low-frequency part and two (horizontal and vertical) edge parts, which are considered as "important" information for human visualization. The low-frequency part is encoded by using block DCT and linear quantization. And the edges are selected by their values and encoded by using Chain coding to remain the most of the important parts for human visualization. At the decoder, the image is reconstructed by first generating the high-frequency parts from the horizontal and vertical edge parts, respectively, and then applying the inverse wavelet transform to the low frequency part and high frequency parts. This composition algorithm has less computational complexity than the conventional analytic/synthetic algorithms because it is not based on iterating approach. Moreover, to reduce the temporal redundancy efficiently, we propose a hierarchical motion detection and a motion interpolation /extrapolation algorithm. We detect motion vectors and motion regions between two reconstructed images and then predict the motion vectors of the current image from the previous detected motion vectors and motion regions by using the interpolation/extrapolation both at the encoder and at the decoder. Therefore, it is unnecessary to transmit the motion vectors and motion regions. This algorithm reduces not only the temporal redundancy but also bit-rates for coding side information . Furthermore, because the motion detection is completely syntax independent, any type of motion detection can be used. We show some simulation results of the proposed video coding algorithm with the coding bit-rate down to 24 kbps and 10 kbps.

Spread-spectrum (SS) sharing with comb spectrum structure in a microcell/macrocell cellular architecture in order to increase spectral efficiency is proposed. Such method employs a filter in the code division multiple access (CDMA) transmitter to feature comb spectrum structure, and suppress interference with a narrowband time division multiple access (TDMA) system in using together in SS sharing. The relationship between microcellular capacity and macrocellular capacity of the system is explored and compared to those of conventional SS sharing and orthogonal sharing. To be concrete, we investigate two cases, i.e., using no power control and ideal power control in the TDMA system. In both cases, the proposed SS sharing gives better capacity results than the conventional SS sharing and in the comparison when ideal power control is used in th. TDMA system, it even has the property to oppose the orthogonal sharing in ideal condition without interference.

Overheads caused by frequently communicating α-β values among numerous parallel search processes not only degrade greatly the performance of existing parallel α-β search algorithm but also make it impractical to implement these algorithms in parallel hardware. To solve this problem, the proposed architecture reduces the overheads by using specially designed multi-value arbiters to compare and global broadcasting buses to communicate α-β values. In addition, the architecture employs a set of α-β search control units (α-β SCU's) with distributed α-β registers to accelerate the search by searching all subtrees in parallel. Simulation results show that the proposed parallel architecture with 1444 (38 38) (α-β SCU's) searching in parallel can achieve 179 folds of speed-up. To verify the parallel architecture, we implemented a VLSI chip with 3 α-β SCU's. The chip can achieve a search speed of 13,381,345 node-visits per second, which is more than three orders of improvement over that of existing parallel algorithms.

Recently, the high-speed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of high-speed error correction circuits. Parallel processing has been found to be an effective method of speeding up operarions, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows H symbols to be processed in parallel, where H is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols H. As an example, we investigate hardware complexity for a Reed-Solomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with H, the proposed architecture is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that a parallel Reed-Solomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.

A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.

The up and coming multimedia services are based on real-time high-speed networks. For efficient operation of such services, real-time and precise network management is essential. In this paper, we show that presently available MIB designs are severely inadequate to support real-time network management. We point out and analyze the management constraints and bottlenecks. The concept of quality of management of management information is introduced and its importance in practical network management is discussed. We have proposed a new MIB architecture that will raise the quality of management information to meet the requirements of managing high-speed networks and multimedia services. Experimental results from a prototype implementation of the new MIB architecture are presented.

This paper presents the results of a simulation study of blocking and non-blocking switching for hierarchical ring networks. The switching techniques include wormhole, virtual cut-through, and slotted ring. We conclude that slotted ring network performs better than the more popular wormhole and virtual cut-through networks. We also show that the size of the node buffers is an important parameter and that choosing them too large can hurt performance in some cases. Slotted rings have the advantage that the choice of buffer size is easier in that larger than necessary buffers do not hurt performance and hence a single choice of buffer size performs well for all system configurations. In contrast, the optimal buffer size for virtual cut-through and wormhole switching nodes varies depending on the system configuration and the level in the hierarchy in which the switching node lies.

This paper discusses a massively parallel interconnection scheme for multithreaded architecture and introduces a new class of direct interconnection networks called the hierarchical Multidimensional Directed Cycles Ensemble (hMDCE). Its suitability for massively parallel systems is discussed. The network is evolved from the Multidimensional Directed Cycles Ensemble (MDCE) network, where each node is substituted by lower-level sub-networks. The new network addresses some serious problems caused by the increasing scale of parallel systems, such as longer latency, limited throughput and high implementation cost. This paper first introduces the MDCE network and then presents and examines in detail the hierarchical MDCE network. Bisection bandwidth of hMDCE is considerably reduced from its ancestor MDCE and the network performs significantly higher throughput and lower latency under some practical implementation constraints. The gate count and delay time of the compiled circuit for the routing function are insignificant. These results reveal that the hMDCE network is an important candidate for massively parallel systems interconnection.

Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The priority-based scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.