The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switched-capacitor circuit is investigated in this work with the sample-and-hold amplifier (SHA) in a 130-nm CMOS process. After overstress on the MOS switch of SHA with unity-gain buffer, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on switch device degrades the circuit performance of bootstrapped switch technique.

The post-annealing process has been investigated for (Ba, Sr)TiO3 [BST] thin films employed as a capacitor dielectric in 1 Gbit dynamic random access memories (DRAMs). The effects of post-annealing on morphology, crystallinity, and dielectric properties were examined for thin film capacitors with BST prepared on Pt electrodes by liquid source chemical vapor deposition (CVD). The direct annealing of BST capacitors caused a roughening in surface morphology of the upper Pt electrodes and BST films. However, the post-annealing of capacitors with a silicon dioxide passivation layer was found to cause little change in surface morphology of Pt and BST, and also no significant deterioration in leakage current. The improvement in crystallinity of BST films through post-annealing was confirmed at a temperature in the range 700-850 by X-ray diffraction (XRD) and transmission electron microscope (TEM). Moreover, the post-annealing experiments for BST films with different compositions showed that the post-annealing greatly increases the dielectric constant of BST films having approximately stoichiometric composition. The leakage and breakdown properties of BST films were also examined, indicating that excess Ti ions result in an increase of the turn-on voltage and the breakdown time. Based on these investigations, the electrical properties of dielectric constant ε 260, equivalent silicon dioxide thickness teq 0. 44 nm, and leakage current JL110-7 A/cm2 at 1. 9 V were successfully obtained for stoichiometric 30-nm-thick BST films post-annealed at 750. Hence, it can be concluded that the post-annealing is a promising technique to enhance the applicability of CVD-deposited BST films with conformal coverage to memory cell capacitors of 1 Gbit DRAMs.

This paper describes the formation of ultra-thin tantalum oxide capacitors, using rapid thermal nitridation (RTN) of the storage-node polycrystalline-silicon surface prior to low-pressure chemical vapor deposition of tantalum oxide, using penta-ethoxy-tantalum [(Ta(OC2H5)5) and oxygen gas mixture. The films are annealed at 600-900 in dry O2 atmosphere. Densification of the as-deposited film by annealing in dry O2 is indispensable to the formation of highly reliable ultra-thin tantalum oxide capacitors. The RTN treatment reduces the SiO2 equivalent thickness and leakage current of the tantalum oxide film, and improves the time dependent dielectric breakdown characteristics of the film.

The dielectric breakdown strength of thermally grown silicon dioxide films was studied for MOS capacitors fabricated on silicon wafers that were intentionally contaminated with magnesium and zinc. Most of magnesium was detected in the oxide film after oxidation. Zinc, some of which evaporated from the surface of wafers, was detected only in the oxide film. The mechanism of the dielectric degradation is dominated by formation of metal silicates, such as Mg2SiO4 (Forsterite) and Zn2SiO4 (Wilemite). The formation of metal silicates has no influence on the generation lifetime of minority carriers, however, it provides the flat-band voltage shift less than 0.3 eV, and forces to increase the density of deep surface states with the zinc contamination.

The dielectric breakdown characteristics of a thin gate oxide during high-current ion implantation with an electron shower have been investigated by controlling the energy distribution of the electrons. Degradation of the oxide has also been discussed with regard to the total charge injected into the oxide during ion implantation in comparison with that of the TDDB (time dependent dielectric breakdown). Experimental results show that the high-energy and high-density electrons which concentrated in the circumference of the ion beam due to the space charge effect cause the degradation of the thin oxide. It was confirmed that eliminating the high-energy electrons by applying magnetic and electric fields lowers the electron energy at the wafer surface, thereby effectively suppressing the negative charge-up.

Breakdown fields and the charges to breakdown (QBD) of oxides increased after UV/Cl2 pre-oxidation cleaning. This is due to decreased residual metal contaminants on silicon surfaces in the bottom of the LOCOS region after wet cleaning. Treatment in NH4OH, H2O2 and H2O prior to UV/Cl2 cleaning suppressed increases in surface roughness and kept leakage currents through the oxides after UV/Cl2 cleaning as low as those after wet cleaning alone. The large junction leakage currents--caused by metal contaminants introduced during dry etching--decreased after UV/Cl2 cleaning which removes the contaminated layer.

The quality of polycrystalline silicon films and electrical characteristics of polycrystalline silicon gate metal-oxide-semiconductor (MOS) capacitors were investigated under various processing conditions, including phosphorus doping. The stresses observed in Si films deposited in the amorphous phase show complex behavior during thermal treatment. The stresses in as-deposited Si films are compressive. They change to tensile with annealing at 800, and to compressive after an additional annealing at 900. The kind of charges trapped in the SiO2 film during the negative constant current stress in Polycrystalline silicon gate MOS capacitors differ with the maximum process temperature. The trapped charges of samples annealed at 800 were negative, while those of samples annealed at 900 were positive.