This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5kΩ contact resistor on the backside of a 350μm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40μm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.

Observed results of arc discharges generated between the brush and commutator are reported. The motion of the arc discharges was observed by a high-speed camera. The brush and commutator were installed to an experimental device that simulated the rotational motion of a real DC motor. The aim of this paper is to investigate the occurring position, dimensions, and moving characteristics of the arc discharges by means of high-speed imaging. Time evolutions of the arc voltage and current were measured, simultaneously. The arc discharges were generated when an inductive circuit was interrupted. Circuit current before interruption was 4A. The metal graphite or graphite brush and a copper commutator were used. Following results were obtained. The arc discharge was dragged on the brush surface and the arc discharge was sticking to the side surface of the commutator. The positions of the arc spots were on the end of the commutator and the center of the brush in rotational direction. The dimensions of the arc discharge were about 0.2 mm in length and about 0.3 mm in width. The averaged arc voltage during arc duration became higher and the light emission from the arc discharge became brighter, as the copper content of the cathode decreased.

Dependences of arc duration D and contact gap at arc extinction d on contact opening speed v are studied for break arcs generated in a 48VDC resistive circuit at constant contact opening speeds. The opening speed v is varied over a wide range from 0.05 to 0.5m/s. Circuit current while electrical contacts are closed I0 is varied to 10A, 20A, 50A, 100A, 200A, and 300A. The following results were obtained. For each current I0, the arc duration D decreased with increasing contact opening speed v. However, the D at I0=300A was shorter than that at I0=200A. On the other hand, the contact gap at arc extinction d tended to increase with increasing the I0. However, the d at I0=300A was shorter than that at I0=200A. The d was almost constant with increasing the v for each current I0 when the I0 was lower than 200A. However, the d became shorter when the v was slower at I0=200A and 300A. At the v=0.05m/s, for example, the d at I0=300A was shorter than that at I0=100A. To explain the cause of the results of the d, in addition, arc length just before extinction L were analyzed. The L tended to increase with increasing current I0. The L was almost constant with increasing the v when the I0 was lower than 200A. However, when I0=200A and 300A, the L tended to become longer when the v was slower. The characteristics of the d will be discussed using the analyzed results of the L and motion of break arcs. At higher currents at I0=200A and 300A, the shorter d at the slowest v was caused by wide motion of the arc spots on contact surfaces and larger deformation of break arcs.

Air discharge immunity testing for electronic equipment is specified in the standard 61000-4-2 of the International Eelectrotechnical Commission (IEC) under the climatic conditions of temperature (T) from 15 to 35 degrees Celsius and relative humidity (RH) from 30 to 60%. This implies that the air discharge testing is likely to provide significantly different test results due to the wide climatic range. To clarify effects of the above climatic conditions on air discharge testing, we previously measured air discharge currents from an electrostatic discharge (ESD) generator with test voltages from 2kV to 15kV at an approach speed of 80mm/s under 6 combinations of T and RH in the IEC specified range and non-specified climatic range. The result showed that the same absolute humidity (AH), which is determined by T and RH, provides almost the identical waveforms of the discharge currents despite different T and RH, and also that the current peaks at higher test voltages decrease as the AH increases. In this study, we further examine the combined effects of air discharges on test voltages, T, RH and AH with respect to two different approach speeds of 20mm/s and 80mm/s. As a result, the approach speed of 80mm/s is confirmed to provide the same results as the previous ones under the identical climatic conditions, whereas at a test voltage of 15kV under the IEC specified climatic conditions over 30% RH, the 20mm/s approach speed yields current waveforms entirely different from those at 80mm/s despite the same AH, and the peaks are basically unaffected by the AH. Under the IEC non-specified climatic conditions with RH less than 20%, however, the peaks decrease at higher test voltages as the AH increases. These findings obtained imply that under the same AH condition, at 80mm/s the air discharge peak is not almost affected by the RH, while at 20mm/s the lower the RH is, the higher is the peak on air discharge current.

This work reports a new technique to suppress the undesirable multiple-triggering effect in the typical diode triggered silicon controlled rectifier (DTSCR), which is frequently used as an ESD protection element in the advanced CMOS technologies. The technique is featured by inserting additional N-Well areas under the N+ region of intrinsic SCR, which helps to improve the substrate resistance. As a consequence, the delay of intrinsic SCR is reduced as the required triggering current is largely decreased and multiple-triggering related higher trigger voltage is removed. The novel DTSCR structures can alter the stacked diodes to achieve the precise trigger voltage to meet different ESD protection requirements. All explored DTSCR structures are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and Very-Fast-Transmission-line-pulsing (VF-TLP) test systems are adopted to confirm the validity of this technique and the test results accord well with our analysis.

In partially depleted SOI (PD-SOI) technology, the SCR-based protection device is desired due to its relatively high robustness, but be restricted to use because of its inherent low holding voltage (Vh) and high triggering voltage (Vt1). In this paper, the body-tie side triggering diode inserting silicon controlled rectifier (BSTDISCR) is proposed and verified in 180 nm PD-SOI technology. Compared to the other devices in the same process and other related works, the BSTDISCR presents as a robust and latchup-immune PD-SOI ESD protection device, with appropriate Vt1 of 6.3 V, high Vh of 4.2 V, high normalized second breakdown current (It2), which indicates the ESD protection robustness, of 13.3 mA/µm, low normalized parasitic capacitance of 0.74 fF/µm.

For the RF power amplifier, its exposed input and output are susceptible to damage from Electrostatic (ESD) damage. The bi-direction protection is required at the input in push-pull operating mode. In this paper, considering the process compatibility to the power amplifier, cascaded Grounded-gate NMOS (ggNMOS) and Polysilicon diodes (PDIO) are stacked together to form an ESD clamp with forward and reverse protection. Through Transmission line pulse (TLP) and CV measurements, the clamp is demonstrated as latch-up immune and low parasitic capacitance bi-direction ESD protection, with 18.67/17.34V holding voltage (Vhold), 4.6/3.2kV ESD protection voltage (VESD), 0.401/0.415pF parasitic capacitance (CESD) on forward and reverse direction, respectively.

This new design uses a low power embedded controller (EC) in cooperation with the BIOS of a notebook (NB) computer, both to accomplish dynamic adjustment and to maintain a required performance level of the battery mode of the notebook. In order to extend the operation time at the battery mode, in general, the notebook computer will directly reduce the clock rate and then reduce the performance. This design can obtain the necessary balance of the performance and the power consumption by using both the EC and the BIOS cooperatively to implement the dynamic control of both the CPU and the GPU frequency to maintain the system performance at a sufficient level for a high speed and high resolution video game. In contrast, in order to maintain a certain notebook performance, in terms of battery life it will be necessary to make some trade-offs.

Break arcs are generated in a 48VDC resistive circuit. Circuit current I0 when electrical contacts are closed is changed from 50A to 300A. The break arcs are observed by a high-speed camera with appropriate settings of exposure from horizontal direction. Length of the break arcs L is measured from images of the break arcs. Time evolutions of the length L and gap voltage Vg are investigated. The following results are obtained. By appropriate settings of the high-speed camera, the time evolution of the length L is obtained from just after ignition to before arc extinction. Tendency of increase of the length L is similar to that of increase of the voltage Vg for each current I0.

In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

Break arcs are rotated with a radial magnetic field formed by a permanent magnet embedded in a fixed contact. The break arcs are generated in a 48VDC resistive circuit. The circuit current is 10A when the contacts are closed. The polarity of the fixed contact in which the magnet is embedded is changed. The rotational radius and the difference of position between the cathode and anode spots are investigated. The following results are obtained. The cathode spot is moved more easily than the anode spot by the radial magnetic field. The rotational radius of the break arcs is affected by the Lorentz force that is caused by the circumferential component of the arc current and the axial component of the magnetic field. The circumferential component of the arc current is caused by the difference of the positions of the rotating cathode and anode spots.

In this paper, the effect of the tilt angle of return stroke channel and the stratified lossy ground on the lightning-induced voltages on the overhead lines are studied using the modified transmission-line model with linear current decay with height (MTLL). The results show that the lightning-induced voltages from oblique discharge channel are larger than those from the vertical discharge channel, and the peak values of the induced voltages will increase with increasing the tilt angle. When the ground is horizontally stratified, the peak of the induced voltages will increase with increasing the conductivity of the lower layer at different distances. When the upper ground conductivity increases, the voltage peak values will decrease if the overhead line is nearby the lightning strike point and increase if the overhead line is far from the lightning strike point. Moreover, the induced voltages are mainly affected by the conductivity of the lower layer soil when the conductivity of the upper layer ground is smaller than that of the lower layer ground at far distances. When the ground is vertically stratified, the induced voltages are mainly affected by the conductivity of the ground near the strike point when the overhead line and the strike point are located above the same medium; if the overhead line and the strike point are located above different mediums, both of the conductivities of the vertically stratified ground will influence the peak of the induced voltages and the conductivity of the ground which is far from the strike point has much more impact on induced voltages.

Improving robustness in electrostatic discharge (ESD) protection by inserting drain-side isolated silicon-controlled rectifiers (SCRs) in a high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device was investigated in this paper. Additionally, the effects of anti-ESD reliability in the HV pLDMOS transistors provided by this technique were evaluated. From the experimental data, it was determined that the holding voltage (Vh) values of the pLDMOS with an embedded npn-arranged SCR and discrete thin-oxide (OD) layout on the cathode side increased as the parasitic SCR OD row number decreased. Moreover, the trigger voltage (Vt1) and the Vh values of the pLDMOS with a parasitic pnp-arranged SCR and discrete OD layout on the drain side fluctuated slightly as the SCR OD-row number decreased. Furthermore, the secondary breakdown current (It2) values (i.e., the equivalent ESD-reliability robustness) of all pLDMOS-SCR npn-arranged types increased (>408.4%) to a higher degree than those of the pure pLDMOS, except for npn-DIS_3 and npn-DIS_2, which had low areas of SCRs. All pLDMOS-SCR pnp-arranged types exhibited an increase of up to 2.2A-2.4A, except for the pnp_DIS_3 and pnp_DIS_2 samples; the pnp_DIS_91 increased by approximately 2000.9% (249.1%), exhibiting a higher increase than that of the reference pLDMOS (i.e., the corresponding pnp-stripe type). The ESD robustness of the pLDMOS-SCR pnp-arranged type and npn-arranged type with a discrete OD layout on the SCR cathode side was greater than that of the corresponding pLDMOS-SCR stripe type and a pure pLDMOS, particularly in the pLDMOS-SCR pnp-arranged type.

This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.

Various DC power supply systems such as photovoltaic power generation, fuel cell and others have been gradually spreading, so that DC power distribution systems are expected as one of energy-saving technologies at houses and business-related buildings as well as data centers and factories. Under such circumstances switches for electric appliances are requested to interrupt DC current safely in DC power systems (DC 300-400V). It is well-known that DC current is much more difficult to be interrupted than AC current with current-zero. In this paper a model switch is developed and fundamental characteristics of DC current interruption in a resistive circuit is experimentally and theoretically examined. Consequently arc duration is found to be approximately a function of interrupted power rather than source voltage and circuit current. In addition arc length at its extinction is obtained by the observation of a high-speed camera. Then the arc length is found to be decided only by interrupted power like the gap length, independent of separation velocity. From these results it can be made clear that the arc form becomes arc-shaped at its extinction when the interrupted power is larger than about 500W. In addition the effect of magnetic blow-out on arc extinction is examined.

Silver contacts are separated at constant speed and break arcs are generated in a 300V-450V DC and 10A resistive circuit. The transverse magnetic field of a permanent magnet is applied to the break arcs. Motion of the break arcs, arc duration and the number of reignitions are investigated when side surfaces of the contacts are covered with insulator pipes. Following results are shown. The motion of the break arcs and the arc duration when the anode is covered with the pipe are the same as those without pipes. When the cathode is covered with the pipe, the motion of break arcs change from that without the pipes and reignitions occur more frequently. The arc duration becomes longer than that without the pipes because of the occurrence of reignitions. The number of reignition increases with increasing the supply voltage in 300V-400V. The period of occurrence of the reignition with pipes is shorter than that when the cathode is covered with the pipe.

Break arcs are rotated with the radial magnetic field formed by a magnet embedded in a fixed cathode contact. The break arcs are generated in a 48VDC resistive circuit. The circuit current when the contacts are closed is 10A. The depth of the magnet varies from 1mm to 4mm to change the strength of the radial magnetic field for rotating break arcs. Images of break arcs are taken by two high-speed cameras from two directions and the rotational motion of the break arcs is observed. The rotational period of rotational motion of the break arcs is investigated. The following results are obtained. The break arcs rotate clockwise on the cathode surface seen from anode side. This rotation direction conforms to the direction of the Lorentz force that affects to the break arcs with the radial magnetic field. The rotational period gradually decreases during break operation. When the depth of magnet is larger, the rotational period becomes longer.

The analytic expressions of lightning electromagnetic fields generated by tortuous channel with an inclined lower section are obtained by decomposing the current infinitesimal and solving Maxwell's equations. By using the transmission line model and pulse function to express the channel-base current, the influence of length and tilt angle of the oblique part on lightning electromagnetic fields as well as the distribution laws of electromagnetic fields for different azimuth angles are analyzed. The results show that the electromagnetic fields in near area are mainly determined by the lower section of the tortuous discharge channel, and the peak values of electromagnetic fields in different field regions will increase with the increasing of the length of the lower section when L1 is shorter than the distance that return-stroke speed multiplied by peak time. Whereas the length of the lower section is longer than the distance that return-stroke speed multiplied by peak time, the waveforms of electromagnetic fields will overlap each other and won't be influenced by oblique part length of the discharge channel before the return-stroke current arrives at the inflection point. Moreover, the peak values of electromagnetic fields will decrease with the increase of tilt angle (the azimuth angle φ = 2π/3) and azimuth angle, and the impact of channel geometry on the electromagnetic field strengthens with the distance.

Layout strategies including source edge to substrate space (SESS) and inserted substrate-pick stripes of gate-grounded NMOS(ggNMOS) are optimized in this work for on-chip electrostatic discharge (ESD) protection. In order to fully investigate influences of substrate resistors on triggering and conduction behaviors of ggNMOS, various devices are designed and fabricated in a 65-nm CMOS process. Direct current (DC), transmission-line-pulsing (TLP), human body model (HBM) and very-fast TLP (VF-TLP) tests are executed to fully characterize performance of fabricated ggNMOS. Test results reveal that an enlarged SESS parameter results in an earlier triggering behavior of ggNMOS, which presents a layout option for subtle adjustable triggering behaviors. Besides, inserted substrate-pick stripes are proved to have a bell-shape influence on the ESD robustness of ggNMOS and this bell-shape influence is valid in TLP, HBM and VF-TLP tests. Moreover, the most ESD-robust ggNMOS optimized under different inserted substrate-pick stripes always achieves a higher HBM level over the traditional ggNMOS at each concerned total device-width. Physical mechanisms of test results will be deeply discussed in this work.

To investigate electrostatic discharge (ESD) immunity testing for wearable electronic devices, the worst scenario i.e., an ESD event occurs when the body-mounted device approaches a grounded conductor is focused in this paper. Discharge currents caused by air discharges from a charged human through a hand-held metal bar or through a semi-sphere metal attached to the head, arm or waist in lieu of actual wearable devices are measured. As a result, it is found that at a human charge voltage of 1kV, the peak current from the semi-sphere metal is large in order of the attachment of the waist (15.4A), arm (12.8A) and head (12.2A), whereas the peak current (10.0A) from the hand-held metal bar is the smallest. It is also found that the discharge currents through the semi-sphere metals decrease to zero at around 50ns regardless of the attachment positions, although the current through the hand-held metal bar continues to flow at over 90ns. These discharge currents are further characterized by the discharge resistance, the charge storage capacitance and the discharge time constant newly derived from the waveform energy, which are validated from the body impedance measured through the hand-held and body-mounted metals. The above finding suggests that ESD immunity test methods for wearable devices require test specifications entirely different from the conventional ESD immunity testing.