Ba0.5Sr0.5Ta2O6 (BSTA) thin film was successfully fabricated on a Pt/SiO2/TiO2/Si substrate using the Sol-Gel method. Fundamental electrical properties of the BSTA thin film were investigated using metal-insulator-metal (MIM) structure. No diffusion of ions, from the thin film or the substrate, is observed because of the using of MIM structure. The Root Mean Square roughness of 1.04 nm shows that thin film grew well on the substrate. The BSTA thin film shows a much higher dielectric constant of about 130 than conventional gate insulators and high-k materials that are currently used in Thin Film Transistors. Low leakage current density of about 10-8 A/cm2 was obtained at an applied electric field of 500 kV/cm. Schottky emission is the dominant conduction mechanism at applied electric fields lower than 500 kV/cm and Fowler-Nordheim tunneling is the dominant conduction mechanism at higher applied electric fields. The Schottky barrier height between the Pt electrode and the Ba0.5Sr0.5Ta2O6 thin film was estimated to be 0.75 eV.

The electrical properties of poly-Si thin film transistors (TFTs) using rapid thermal annealing with various gate oxide thicknesses were studied in this work. It was found that Poly-Si TFT electrical characteristics with the thinnest gate oxide thickness after RTA treatment exhibits the largest performance improvement compared to TFT with thick oxide as a result of the increased incorporated amounts of the nitrogen and oxygen. Thus, the combined effects can maintain the advantages and avoid the disadvantages of scaled-down oxide, which is suitable for small-to-medium display mass production.

In many different bioelectronic applications silicon field-effect devices such as transistors or nanowires are used. Usually native or thermally grown silicon oxides serve as interfacing layer to the liquid. For an effective voltage to current conversion of the devices, the main demands for interface layers are low leakage current, low defect density, and high input capacitance. In this article we describe the fabrication and characterization of ultra-thin silicon oxide/high-κ material stacks for bioelectronics. A combination of ultra-thin silicon oxide and DyScO3 revealed the best results. This material stack is particularly interesting for future fabrication of field-effect devices for bioelectronic applications.

We present the effects of N2O plasma treatment for hot carrier reliability and gate oxide stability in excimer-laser annealed poly-Si TFTs. N2O plasma treatment between SiO2 and poly-Si suppresses both the reduction in mobility caused by hot carrier stress and the Vth shift caused by gate bias stress. The results of XPS spectra and the energy distribution of the trap state density of stressed TFTs show that the introduction of Si-N bonds plays an important role in poly-Si TFT reliability.

A new test structure to specify accurately the position of gate oxide breakdown is proposed, which simply consists of a conventional polycrystalline Si gate MOS capacitor and Al dots array diagonally lined-up on the capacitor. Optical beam induced current microscope was used to discriminate the breakdown spot. Layout of the discriminated spot among the Al dot array accurately determined the breakdown position. A 5-nm-thick gate oxide breakdown spot determined by this method has been successfully investigated by cross-sectional transmission electron microscopy (XTEM). A series of site-specified XTEM studies reveal local melting of anode Si during the intrinsic dielectric breakdown. This test structure is practically useful for site-specified XTEM studies on process-induced degradation phenomena of thin gate oxides.

The gate oxide of sub-0.1 µm MOSFETs channel length is expected to be reduced beyond 3 nm in spite of an increasing direct tunneling gate current. As tunnel injection modeling into SiO2 is expected to depend on the electron transport model adopted for the device description, a critical comparison is made in this paper between gate currents obtained from simulators based on Drift-Diffusion, Energy-Balance, and Monte Carlo models. The studied device is a 0.07 µm channel length n-MOSFET with 1.5 nm thick gate oxide. It is shown that positive drain voltage is responsible for two opposite effects on DT leakage: a carrier heating and a potential barrier hardening along the channel. It is proved by a careful study of Monte Carlo microscopic quantities that, contrary to what holds for thicker gate oxide transistors, the balance is favorable to the potential barrier effect. Injection into SiO2 is then dominated by near-thermal carriers injected at the channel beginning. For this reason, the gate current decreases when increasing the drain bias, with the maximum leakage obtained for (Vgs=Vdd, Vds=0), and a correct agreement is obtained between the Drift-Diffusion, Energy-Balance, and Monte Carlo approaches of gate current calculation, in spite of very different physical descriptions of transport at the microscopic level.

High-frequency capacitance-voltage (C-V) characteristics of buried-channel MOS capacitors with a structure of subquarter-micron pMOS have been measured and analyzed, emphasizing transient behavior. The C-V characteristics, including transient behavior, of buried-channel MOS capacitors that have a counter-doped p layer at the surface of n substrate are very similar to those of surface-channel MOS capacitors of n substrate if the counter-doped layer is shallow enough to be fully inverted at large positive bias. As gate voltage is decreased, equilibrium capacitance for inversion (accumulation for the counter-doped layer) reaches a minimum value and then slightly increases to saturate, which is peculiar to buried-channel capacitors. The gate voltage for minimum capacitance, which has been used to estimate the threshold voltage, changes dramatically by illumination even in room light. Net doping profiles of n-type dopant can be obtained from pulsed C-V characteristics even for buried-channel capacitors. For MOS capacitors with thinner gate oxide (5 nm), steady-state C-V curve is not an equilibrium one but a deep depletion one at room temperature. This is because holes are drained away by tunneling through the thin gate oxide.

Plasma damage to gate oxide is studied using the test structures with various length antennas. It is shown that the plasma damage to gate oxide can be monitored quantitatively by measuring charge to breakdown (QBD). From the QBD measurements, it is confirmed that the degradation occurs in the duration of over-etching but not in the duration of main etching. The breakdown spots in gate oxide are detected by a photon emission method. The breakdown are caused by plasma damage at the LOCOS edge. A LOCOS structure plays an important role for the degradation by the plasma damage.

A new technique for evaluating gate oxide reliability using photon emission method has been developed. This method enables the measurements of the initial breakdown characteristics, reliability testing and failure analysis consistently. From the experimental results, followings are clarified for the first time using this technique. Failure modes in the initial characteristics have close correlation to TDDB characteristics and both characteristics correspond to the location of breakdown spot. The results suggest measures to improve the reliability of gate oxide and the existance of new failure mechanism.

The quality of polycrystalline silicon films and electrical characteristics of polycrystalline silicon gate metal-oxide-semiconductor (MOS) capacitors were investigated under various processing conditions, including phosphorus doping. The stresses observed in Si films deposited in the amorphous phase show complex behavior during thermal treatment. The stresses in as-deposited Si films are compressive. They change to tensile with annealing at 800, and to compressive after an additional annealing at 900. The kind of charges trapped in the SiO2 film during the negative constant current stress in Polycrystalline silicon gate MOS capacitors differ with the maximum process temperature. The trapped charges of samples annealed at 800 were negative, while those of samples annealed at 900 were positive.