In this paper, we propose a true random number generator (TRNG) exploiting jitter and the chaotic behavior in cross ring oscillators (CROs). We make a further study of the feedback ring architecture and cross-connect the XOR gates and inverters to form an oscillator. The CRO utilizes totally digital logic circuits, and gains a high and robust entropy rate, as the jitter in the CRO can accumulate locally between adjacent stages. Two specific working modes of CRO in which the CRO can work in a consistent state and a free-running state respectively are introduced and analyzed both theoretically and experimentally. Finally, different stage lengths of cross ring true random number generators (CRTRNGs) are tested in different Field Programmable Gate Arrays (FPGAs) and test results are analyzed and compared. Especially, random data achieved from a design of 63-stage CRTRNG in Altera Cyclone IV passes both the NIST and Diehard test suites at a rate as high as 240Mbit/s.

In this article, we investigate the depth distribution and the depth spectra of linear codes over the ring R=F2+uF2+u2F2, where u3=1. By using homomorphism of abelian groups from R to F2 and the generator matrices of linear codes over R, the depth spectra of linear codes of type 8k14k22k3 are obtained. We also give the depth distribution of a linear code C over R. Finally, some examples are presented to illustrate our obtained results.

This paper deals with the security of chaos-based “true” random number generators (RNG)s. An attack method is proposed to analyze the security weaknesses of chaos-based RNGs and its convergence is proved using a master slave synchronization scheme. Attack on a RNG based on a double-scroll attractor is also presented as an example. All secret parameters of the RNG are revealed where the only information available is the structure of the RNG and a scalar time series observed from the double-scroll attractor. Simulation and numerical results of the proposed attack method are given such that the RNG doesn't fulfill NIST-800-22 statistical test suite, not only the next bit but also the same output bit stream of the RNG can be reproduced.

In this article, we study skew cyclic codes over $R=mathbb{F}_{q}+vmathbb{F}_{q}+v^{2}mathbb{F}_{q}$, where $q=p^{m}$, $p$ is an odd prime and v3=v. We describe the generator polynomials of skew cyclic codes over this ring and investigate the structural properties of skew cyclic codes over R by a decomposition theorem. We also describe the generator polynomial of the dual of a skew cyclic code over R. Moreover, the idempotent generators of skew cyclic codes over $mathbb{F}_{q}$ and R are considered.

A forward/reverse body bias generator (BBG) which operates under wide supply-range is proposed. Fine-grained body biasing (FGBB) is effective to reduce variability and increase energy efficiency on digital LSIs. Since FGBB requires a number of BBGs to be implemented, simple design is preferred. We propose a BBG with charge pumps for reverse body bias and the BBG operates under wide supply-range from 0.5,V to 1.2,V. Layout of the BBG was designed in a cell-based flow with an AES core and fabricated in a 65~nm CMOS process. Area of the AES core is 0.22 mm$^2$ and area overhead of the BBG is 2.3%. Demonstration of the AES core shows a successful operation with the supply voltage from 0.5,V to 1.2,V which enables the reduction of power dissipation, for example, of 17% at 400,MHz operation.

A readout technique using single-flux-quantum (SFQ) circuits enables superconducting single photon detectors (SSPDs) to operate at further high-speed, where a mutually-coupled dc-to-SFQ (MC-dc/SFQ) converter is used as an interface between SSPDs and SFQ circuits. In this work, we investigated pulse response of the MC-dc/SFQ converter. We employed on-chip pulse generators to evaluate pulse response of the MC-dc/SFQ converter for various pulses. The MC-dc/SFQ converter correctly operated for the pulse current with the amplitude of 52,$mu$A and the width of 179,ps. In addition, we examined influence of the pulse amplitude and width to operation of the MC-dc/SFQ converter by numerical simulation. The simulation results indicated that the MC-dc/SFQ converter had wide operation margins for pulse current with amplitudes of 30--60,$mu$A irrespective of the pulse widths.

We proposed a hard-wired CPG hardware network to reproduce the gaits of four-legged animals. It should reproduce walking and bounding, and they should be switchable with each other by changing the value of only one voltage.

A serial ATA PHY fabricated in a 0.15-µm CMOS process performs the serial ATA operation in an asynchronous transition by using large variation in the reference clock. This technique calibrates a transmission signal frequency by utilizing the received signal. This is achieved by calibrating the divide ratio of a spread-spectrum clock generator (SSCG). This technique enables a serial ATA PHY to use reference oscillators with a production-frequency tolerance of less than 400ppm, i.e., higher than the permissible TX frequency variations (i.e., 350ppm). The calibrated transmission signal achieved a total jitter of 3.9ps.

Electrostatic discharge (ESD) generators cause electromagnetic (EM) noises not only at ESD tests but also even before and after the tests. This may provide inconsistent test results, but the mechanism has not been well examined. To explain the mechanism qualitatively, we investigated a generation source model of EM noises from an ESD generator in conjunction with the functional control sequences of built-in relay switches and the DC high voltage power supply. To validate this model, we used a magnetic field probe to measure the induced EM noises before, during, and after contact and air discharges in accordance with the corresponding timing of the functional control sequences. As a result, we confirmed that the EM noises are induced when the relay switches operate before and at ESD testing and after ESD tests for both contact and air discharges. In addition, we found that the noise peaks due to contact discharges increase with charge voltages, and the peaks just before and at the testing are relatively larger than the ones after the tests, while the peaks of the induced noises at the air discharge testing do not always increase with charge voltages, but reach a maximum at 3kV. In addition, the peaks of the induced noises at the air discharge testing become smaller than either the peaks just before the testing and those after the tests at charge voltages above 6kV. This suggests that the EM noises just before ESD testing and after the test may cause the EUT to malfunction when air discharge tests with charge voltages over 6kV are conducted. A new control sequence of the built-in relay switch was also proposed for reducing the EM noises after ESD tests, which was validated through noise measurements.

This paper presents an oscillator-based true random number generator (TRNG) that dynamically unbiases 0/1 probability. The proposed TRNG automatically adjusts the duty cycle of a fast oscillator to 50%, and generates unbiased random numbers tolerating process variation and dynamic temperature fluctuation. A prototype chip of the proposed TRNG was fabricated with a 65nm CMOS process. Measurement results show that the developed duty cycle monitor obtained the probability of ‘1’ 4,100 times faster than the conventional output bit observation, or estimated the probability with 70 times higher accuracy. The proposed TRNG adjusted the probability of ‘1’ to within 50±0.07% in five chips in the temperature range of 0°C to 75°C. Consequently, the proposed TRNG passed the NIST and DIEHARD tests at 7.5Mbps with 6,670µm2 area.

This paper presents a comparative study of the number of pieces of optical transport equipment, network cost and power consumption depending on the transmission reach of the 400-Gb/s-based signal between flexible-bitrate networks using 100-Gb/s and 400-Gb/s signals and 100-Gb/s-based single-line-rate networks. In this study, we use three types of network topologies: a North American network topology, a European network topology and a Japan photonic network topology. As for the transmission reach of the 400-Gb/s-based signal, considering performance margins, different transmission reaches of the 400-Gb/s signal are assumed varying from 300km to 600km with 100-km increments. We show that the 100-Gb/s and 400-Gb/s-based flexible-bitrate networks are effective for cutting the total number of pieces of equipment and could be effective for reducing network cost and power consumption depending on the transmission reach of the 400-Gb/s signal in the case of a relatively small-scale network.

The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (PG) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-µm CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.

Generalized quasi-cyclic (GQC) codes with arbitrary lengths over the ring $mathbb{F}_{q}+umathbb{F}_{q}$, where u2=0, q=pn, n a positive integer and p a prime number, are investigated. By the Chinese Remainder Theorem, structural properties and the decomposition of GQC codes are given. For 1-generator GQC codes, minimum generating sets and lower bounds on the minimum distance are given.

A body bias generator (BBG) for fine-grained body biasing (FGBB) is proposed. The FGBB is effective to reduce variability and power consumption in a system-on-chip (SoC). Since FGBB needs a number of BBGs, the BBG is preferred to be implemented in cell-based design procedure. In the cell-based design, it is inefficient to provide an extra supply voltage for BBGs. We invented a BBG with switched capacitor configuration and it enables BBG to operate with wide range of the supply voltage from 0.6V to 1.2V. We fabricated the BBG in a 65nm CMOS process to control 0.1mm2 of core circuit with the area overhead of 1.4% for the BBG.

This paper presents an implementation of a digital chaotic signal generator based on compound one-dimensional sinusoidal maps. The proposed chaotic map not only offers high chaoticity measured from a positive lyapunov exponent but also provides diverse bifurcation structures with robust chaos over most regions of parameter spaces. Implementation on FPGA realizes small number of components and offers a highly random chaotic sequence with no autocorrelation. The proposed chaotic signal generator offers a potential alternative in random test pattern generation or in secured data communication applications.

This paper introduces a comparison of three automatic gait generation methods for quadruped robots: GA (Genetic Algorithm), GP (genetic programming) and CPG (Central Pattern Generator). It aims to provide a useful guideline for the selection of gait generation methods. GA-based approaches seek to optimize paw locus in Cartesian space. GP-based techniques generate joint trajectories using regression polynomials. The CPGs are neural circuits that generate oscillatory output from an input coming from the brain. Optimizations for the three proposed methods are executed and analyzed using a Webots simulation of the quadruped robot built by Bioloid. The experimental comparisons and analyses provided herein will be an informative guidance for research of gait generation method.

In this paper we propose a unified coprocessor architecture that, by using a Glitch PUF and a block cipher, efficiently unifies necessary functions for secure key storage and challenge-response authentication. Based on the fact that a Glitch PUF uses a random logic for the purpose of generating glitches, the proposed architecture is designed around a block cipher circuit such that its round functions can be shared with a Glitch PUF as a random logic. As a concrete example, a circuit structure using a Glitch PUF and an AES circuit is presented, and evaluation results for its implementation on FPGA are provided. In addition, a physical random number generator using the same circuit is proposed. Evaluation results by the two major test suites for randomness, NIST SP 800-22 and Diehard, are provided, proving that the physical random number generator passes the test suites.

A technique that enables a SSCG to fine-tune an output signal frequency and a spread ratio is presented. Proposed SSCG achieves the output signal frequency from 1.2 GHz to 3.0 GHz and the spread ratio from 0 to 30000 ppm. The fine-tuning technique achieves 30 ppm adjustment of the output signal frequency and 200 ppm adjustment of the spread ratio. This technique is achieved by controlling a triangular modulation signal characteristics generated by a proposed digital controlled wave generator. A proposed multi-modulus divider can have a divide ratio of 4/5 and 8/9. This SSCG has been fabricated in a 0.13-µm CMOS process. The output signal frequency-range and the spread ratio are achieved fluently from 0.1 to 3.0 GHz and from 0 to 30000 ppm, respectively. EMI noise is suppressed at less than 17.1 dB at the output signal frequency of 3.0 GHz and spread ratio of 30000 ppm.

This paper introduces the basics of energy harvesters and demonstrates two specific vibratory-type energy harvesters developed at the University of Hyogo. The fabrication and evaluation results of the vibratory-type energy harvesters, which employ electrostatic and electromagnetic mechanisms, are described. The aim of developing these devices is to realize a power source for an autonomous human monitoring system. The results of harvesting from actual human activities obtained using a data logger are also described. Moreover, challenges in the power management of electronic circuitry used for energy harvesting are briefly discussed.

This paper describes algorithms for generating low intermodulation-distortion (IMD) two-tone sinewaves, for such as communication application ADC testing, using an arbitrary waveform generator (AWG) or a multi-bit ΣΔ DAC inside an SoC. The nonlinearity of the DAC generates distortion components, and we propose here eight methods to precompensate for the IMD using DSP algorithms and produce low-IMD two-tone signals. Theoretical analysis, simulation, and experimental results all demonstrate the effectiveness of our approach.