The three-bit balanced ternary quantum voltage generator was designed and tested. This voltage generator is based on zero-crossing Shapiro steps (ZCSSs) in asymmetric two-junction SQUID. ZCSSs were observed on the current-voltage curves, and maximum and minimum current of ZCSSs were almost same, respectively for the three bits. 27-step quantum voltages from -13Φ0f to +13 Φ0f were observed by combinations of inputs of bit1, bit2 and bit3.

We propose a jitter amplifier architecture for an oscillator-based true random number generator (TRNG). Two types of latency-controllable (LC) buffer, which are the key components of the proposed jitter amplifier, are presented. We derive an equation to estimate the gain of the jitter amplifier, and analyze sufficient conditions for the proposed circuit to work properly. The proposed jitter amplifier was fabricated with a 65 nm CMOS process. The jitter amplifier with the two-voltage LC buffer occupied 3,300 µm2 and attained 8.4x gain, and that with the single-voltage LC buffer achieved 2.2x gain with an 1,700 µm2 area. The jitter amplification of the sampling clock increased the entropy of a bit stream and improved the results of the NIST test suite so that all the tests passed whereas TRNGs with simple correctors failed. The jitter amplifier attained higher throughput per area than a frequency divider when the required amount of jitter was more than two times larger than the inherent jitter in our test-chip implementations.

Dynamic resource management has become an active area of research in the Cloud Computing paradigm. Cost of resources varies significantly depending on configuration for using them. Hence efficient management of resources is of prime interest to both Cloud Providers and Cloud Users. In this work we suggest a probabilistic resource provisioning approach that can be exploited as the input of a dynamic resource management scheme. Using a Video on Demand use case to justify our claims, we propose an analytical model inspired from standard models developed for epidemiology spreading, to represent sudden and intense workload variations. We show that the resulting model verifies a Large Deviation Principle that statistically characterizes extreme rare events, such as the ones produced by “buzz/flash crowd effects” that may cause workload overflow in the VoD context. This analysis provides valuable insight on expectable abnormal behaviors of systems. We exploit the information obtained using the Large Deviation Principle for the proposed Video on Demand use-case for defining policies (Service Level Agreements). We believe these policies for elastic resource provisioning and usage may be of some interest to all stakeholders in the emerging context of cloud networking.

This paper investigates a clock frequency generator for ultra-low-voltage sub-picosecond-jitter clock generation in future 0.5-V LSI and power aware LSI. To address the potential possible solution for ultra-low-voltage applications, a 0.5 V clock frequency generator is proposed and implemented. Significant performances, in terms of sub 1-ps jitter, 50 MHz-to-6.4 GHz frequency tuning range with 2 bands and sub 1-mW PDC, demonstrated the viable replacement of ring oscillators in low-voltage and low-jitter clock generator.

A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.

In this paper, we derive a simple formula to generate a wide-sense systematic generator matrix(we call it quasi-systematic) B for a Reed-Solomon code. This formula can be utilized to construct an efficient interpolation based erasure-only decoder with time complexity O(n2) and space complexity O(n). Specifically, the decoding algorithm requires 3kr + r2 - 2r field additions, kr + r2 + r field negations, 2kr + r2 - r + k field multiplications and kr + r field inversions. Compared to another interpolation based erasure-only decoding algorithm derived by D.J.J. Versfeld et al., our algorithm is much more efficient for high-rate Reed-Solomon codes.

Recently, the GMPLS controlled WSON has emerged as a promising optical transport network. In order to guarantee the optical signal transmission feature without deformation, the optoelectronic 3R regenerators still need to be sparsely placed in the network, termed as translucent networks. The growing size and complexity of the translucent network requires a transition of control plane to move from the traditional centralized model to a fully distributed architecture in the future. However, centrally designed routing, wavelength assignment, and 3R regenerator allocation approaches become unfeasible under the distributed paradigm due to the outdated and inconsistent network state information. A common solution is to accelerate the update frequency of network state, but the fundamental problem remains that the inaccurate state information is still inevitable. Furthermore, it adds a significant increase to the control traffic volume which adversely degrades the performance and scalability of the network control system. In order to mitigate the impact of having inaccurate state information on network performance in the distributed systems, a novel RWA approach is proposed in this paper, termed as routing and distributed wavelength assignment with top ranked probing wavelength set computation. In our proposal, the wavelength assignment is performed by signalling process with a set of carefully preselected probing wavelengths. This set is dynamically computed based on the resource utilization each time the network state is refreshed. The PCE module is adopted in WSON control plane to be responsible for the computation of RWA and 3R allocation. The performance of the proposed approach is studied by extensive simulations. The experiment results reveal that by employing the proposed scheme, without loss on the blocking performance the inaccuracy of the wavelength availability information can be well tolerated, and the set-up delay in lightpath provisioning can be kept at a low level.

This paper presents the analytical results of the effects of jitter and intersymbol interference (ISI) on a millimeter-wave impulse radio (IR) transceiver, compared with the performance of a developed 10-Gb/s W-band IR-transmitter prototype. The IR transmitter, which is compact and cost-effective, consists of a pulse generator (PG) that creates an extremely short pulse, a band-pass filter (BPF) that shapes the short pulse to the desired millimeter-wave pulse (wavelet), and an optional power amplifier. The jitters of the PG and ISI from the BPF are a hindrance in making the IR transceiver robust and in obtaining excellent performance. One analysis verified that, because of a novel retiming architecture, the random jitter and the data-dependent jitter from the PG give only a small penalty of < 0.5-dB increase in the signal-to-noise ratio (SNR) for achieving a bit error rate (BER) of < 10-12. An alternative analysis on the effect of ISI from the BPF indicated that using a Gaussian BPF enables a transmission with a BER of < 10-12 up to a data rate of 1.4 times as large as the bandwidth of the BPF, which is twice as high as that of a conventional amplitude shift keying (ASK) system. The analysis also showed that the IR system is more sensitive to the ISI than the ASK system and suggested that the mismatching of the skirt characteristics of the developed BPF with those of a Gaussian BPF causes tail lobes following the wavelet, resulting in an on/off ratio of 15 dB and hence, an SNR penalty of 6 dB.

In this letter, we propose an appealing class of nonbinary quasi-cyclic low-density parity-check (QC-LDPC) cycle codes. The parity-check matrix is carefully designed such that the corresponding generator matrix has some nice properties: 1) systematic, 2) quasi-cyclic, and 3) sparse, which allows a parallel encoding with low complexity. Simulation results show that the performance of the proposed encoding-aware LDPC codes is comparable to that of the progressive-edge-growth (PEG) constructed nonbinary LDPC cycle codes.

In this paper, a new algorithm called TGA is introduced which defines the concept of time more naturally for the first time. A parameter called TimeToLive is considered for each chromosome, which is a time duration in which it could participate in the process of the algorithm. This will lead to keeping the dynamism of algorithm in addition to maintaining its convergence sufficiently and stably. Thus, the TGA guarantees not to result in premature convergence or stagnation providing necessary convergence to achieve optimal answer. Moreover, the mutation operator is used more meaningfully in the TGA. Mutation probability has direct relation with parent similarity. This kind of mutation will decrease ineffective mating percent which does not make any improvement in offspring individuals and also it is more natural. Simulation results show that one run of the TGA is enough to reach the optimum answer and the TGA outperforms the standard genetic algorithm.

A novel random number generation method based on chaotic sampling of regular waveform is proposed. A high speed IC truly random number generator based on this method is also presented. Simulation and experimental results, verifying the feasibility of the circuit, are given. Numerical binary data obtained according to the proposed method pass the four basic tests of FIPS-140-2, while experimental data pass the full NIST-800-22 random number test suite without post-processing.

A sanitizable signature scheme is a signature scheme which, after the signer generates a valid signature of a message, allows a specific entity (sanitizer) to modify the message for hiding several parts. Existing sanitizable signature schemes require the message to be divided into pre-defined blocks before signing so that each block can be sanitized independently. However, there are cases where the parts of the message which are needed to be sanitized can not be determined in the time of signing. Thus, it is difficult to decide the partition of the blocks in such cases. Since the length of the signature is usually proportional to the number of blocks, signing every bit independently will make the signature too long. In this paper, we propose a solution by introducing a new concept called sequential bitwise sanitizable signature schemes, where any sequence of bits of the signed document can be made sanitizable without pre-defining them, and without increasing the length of signature. We also show that a one-way permutation suffices to get a secure construction, which is theoretically interesting in its own right, since all the other existing schemes are constructed using stronger assumptions.

A 4-phase clock generator, which can dynamically change clock frequencies, duty ratios and I/Q balance, is proposed for on-chip timing margin testing. The clock generator macro is integrated into the microprocessor chip of the supercomputer SX-9, which is fabricated with a 65 nm CMOS technology. It demonstrates frequency syntheses of 1.68 GHz to 3 GHz range, an instant frequency change capability for timing margin testing, duty ratio and I/Q balance adjustments of -12.5 ps to 9.4 ps with a 3.125 ps step resolution.

This paper proposes a high-speed architecture to realize two-variable numeric functions. It represents the given function as an edge-valued multiple-valued decision diagram (EVMDD), and shows a systematic design method based on the EVMDD. To achieve a design, we characterize a numeric function f by the values of l and p for which f is an l-restricted Mp-monotone increasing function. Here, l is a measure of subfunctions of f and p is a measure of the rate at which f increases with an increase in the dependent variable. For the special case of an EVMDD, the EVBDD, we show an upper bound on the number of nodes needed to realize an l-restricted Mp-monotone increasing function. Experimental results show that all of the two-variable numeric functions considered in this paper can be converted into an l-restricted Mp-monotone increasing function with p=1 or 3. Thus, they can be compactly realized by EVBDDs. Since EVMDDs have shorter paths and smaller memory size than EVBDDs, EVMDDs can produce fast and compact NFGs.

We propose a randomness test based on the T-complexity of a sequence, which can be calculated using a parsing algorithm called T-decomposition. Recently, the Lempel-Ziv (LZ) randomness test based on LZ-complexity using the LZ78 incremental parsing was officially excluded from the NIST test suite in NIST SP 800-22. This is caused from the problem that the distribution of P-values for random sequences of length 106 is strictly discrete for the LZ-complexity. Our proposed test can overcome this problem because T-complexity has almost ideal continuous distribution of P-values for random sequences of length 106. We also devise a new sequential T-decomposition algorithm using forward parsing, while the original T-decomposition is an off-line algorithm using backward parsing. Our proposed test can become a supplement to NIST SP 800-22 because it can detect several undesirable pseudo-random numbers that the NIST test suite almost fails to detect.

A low power pulse generator design using hybrid logic realization of a 3-input NAND gate is presented. The hybrid logic approach successfully shortens the critical path along the discharging transistor stack and thus reduces the short circuit power consumption during the pulse generation. The combination of pass transistor and full CMOS logic styles in one NAND gate design also helps minimize the required transistor size, which alleviates the loading capacitance of clock tree as well. Simulation results reveal that, compared with prior work, our design can achieve 20.5% and 23% savings respectively in power and circuit area.

A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13 µm CMOS technology, and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146 µW at 304 MHz.

This paper presents two power-saving designs for Quadratic Polynomial Permutation (QPP) interleave address generator of which interleave length K is fixed and unfixed, respectively. These designs are based on our observation that the quadratic term f2x2%K of f(x) = (f1x+f2x2)%K, which is the QPP address generating function, has a short period and is symmetric within the period. Power consumption is reduced by 27.4% in the design with fixed-K and 5.4% in the design with unfixed-K on the average for various values of K, when compared with existing designs.

This paper proposes a new chaos generator circuit with a current sampling scheme. This circuit generates an arbitrary nonlinear function corresponding to the time-domain current waveform supplied from an external source by using a pulse phase modulation approach. The measurement results of a fabricated chip with TSMC 0.25 µm process technology demonstrate that the proposed circuit can generate chaos signals even if D/A conversion is used for nonlinear waveform generation, because a current integral by sampling with a short pulse smooths the quantized nonlinear function.

This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13 µm CMOS process achieves 105 MHz to 225 MHz of clock frequency while consuming 4.2 mW from 1.2 V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8 ps and 0.031% at 105 MHz, respectively.