In arithmetic units multiplication is a very important operation. It is a common approach to use the modified Booth's algorithm to reduce the number of partial products in a multiplication and speed it up. In this letter we show two circuits that fuse the usually separate functions of generating the partial products and selecting them. The circuits designed in DPL (Double Pass-transistor Logic) are bigger in MOS transistors, but are faster and, function at higher frequencies than a typical CMOS implementation. One of our circuits also has lower power consumption.

This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-time (TAT) is dramatically reduced. Experimental results for the 110 k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.

In this paper, we develop parallel scrambling techniques for the distributed sample scrambling (DSS), which are directly applicable to the bit- and multibit-interleaved multiplexing environments. We first consider how to realize PSRGs, parallel samplings and parallel corrections for the multibit-parallel DSS (MPDSS), which are the fundamental problems in realizing the MPDSS scramblers and descramblers. The results are summarized in three sets of theorems, and a corollary is attached to each theorem to specifically handle the case of the parallel DSS (PDSS). The theorems and corollaries are supported by examples that demonstrate the relevant MPDSS scramblers and descramblers.

A method to design one-dimensional cellular arrays to be used as TPG circuits of BIST is described. The interconnections between cells are not limited to adjacent ones but allowed to some neighbors. Completely regular structures that have full-transition coverages for every k-dimensional subspace of state variables are first shown. Then, almost regular arrays which can operate on maximum cycles are derived based on fast parallel implementations of LFSRs.

This letter is concerned with 2k-ary cyclic AN codes for burst error correction. We present the relation between the burst error correcting ability of a binary cyclic AN code and that of a 2k-ary cyclic AN code when these codes are generated by the same generator A.

A composite noise generator (CNG) is proposed for simulating the actual non-Gaussian noise and its applications are mentioned. Basing upon the actual measured result (APD) of induced noise from electric contact discharge arc, the APD is approximated by partial linearlization and shown that it can be simulated by a combination of plural Gaussian noise sources. Applying the CNG, quasi-peak (Q-P) detector is investigated and shown that the Q-P detector response is different for non-Gaussian noise when its time domain parameter is different even if its original APD is the same. For digital transmission error due to non-Gaussian noise, and for TV picture stained by the non-Gaussian noise, the CNG is applied to evaluate their performances and quality. The results obtained show that the CNG can be used as a standard non-Gaussian generator for several immunity tests for information equipments.

Feasibility of 20 Gbit/s single channel transoceanic soliton transmission systems with a simple EDFA repeaters configuration has been studied. Both a simple and versatile soliton pulse generator and a polarization insensitive optical demultiplexer, which can provide a almost square shape optical gate with duration of full bit time period, have been proposed and demonstrated by using sinusoidally modulated electroabsorption modulators. The optical time-division multiplexing/demultiplexing scheme using the optical demultiplexer results in drastic improvement of bit error rate characteristics. We have experimentally confirmed that the use of alternating-amplitude solitons is an efficient way to mitigate not only soliton-soliton interaction but also Gordon-Haus timing jitter constraints in multi-ten Gbit/s soliton transmission. Timing jitter reduction using relatively wide band optical filter bas been investigated in 20 Gbit/s loop experiments and single-carrier, single-polarization 20 Gbit/s soliton data transmission over 11500 km with bit error rate of below 10-9 has been experimentally demonstrated, using the modulator-based soliton source, the optical demultiplexer, the alternation-amplitude solitons, and wide-band optical filters. Obtained 230 Tbit/skm transmission capacity shows the feasibility of 20 Gbit/s single channel soliton transoceanic systems using fully practical technologies.

A programmable clock generator, based on a phase-locked loop (PLL) circuit, has been developed with 0.5 µm CMOS triple-layer Al interconnection technology for use as an on-chip clock generator in a 300-MHz video signal processor. The PLL-based clock generator generates a clock signal whose frequency ranges from 50 to 350 MHz which is an integral multiple, from 2 to 16, of an external clock frequency. In order to achieve stable operation within this wide range, a voltage controlled oscillator (VCO) with selectable low VCO gain characteristics has been developed. Experimental results show that the clock generator generates a 297-MHz clock with a 27-MHz external clock, with jitter of 180 ps and power dissipation of 120 mW at 3.3-V power supply, and it can also oscillate up to 348 MHz with a 31.7-MHz external clock.

A 3.2 GHz, 50 mW, 1 V, GaAs clock pulse generator (CG) based on a phase-locked loop (PLL) circuit has been designed for use as an on-chip clock generator in future high speed processor LSIs. 0.5 µm GaAs MESFET and DCFL circuit technologies have been used for the CG, which consists of 224 MESFETs. An "enhanced charge-up current" inverter has been specially designed for a low power and high speed voltage controlled oscillator (VCO). In this new inverter, a voltage controlled dMESFET is combined in parallel with the load dMESFET of a conventional DCFL inverter. This voltage controlled dMESFET produces an additional charge-up current resulting in the new VCO obtaining a much higher oscillation frequency than that of a ring oscillator produced with a conventional inverter. With a single 1 V power supply (Vdd), SPICE calculation results showed that the VCO tuning range was 2.25 GHz to 3.65 GHz and that the average VCO gain was approximately 1.4 GHz/V in the range of a control voltage (Vc) from 0 to 1 V. Simulation also indicated that at a Vdd of 1 V the CG locked on a 50 MHz external clock and generated a 3.2 GHz internal clock (=50 MHz64). The jitter and power dissipation of the CG at 3.2 GHz oscillation and a Vdd of 1 V were less than 8.75 psec and 50 mW, respectively. The typical lock range was 2.90 GHz to 3.59 GHz which corresponded to a pull-in range of 45.3 MHz to 56.2 MHz.

Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.

We propose a new multiple folding algorithm for the gate matrix layout, and apply it to generation of rectangular blocks with flexible size. The algorithm consists of two phases, the net partitioning and the gate arangement, and both algorithms are based on the multi-way mini-cut technique. In the first and second phases, the width and height of the multiple folded gate matrix block are directly minimized, resperctively, such that the area is minimized and desired aspect ratio of the block is obtained. The features of the present algorithm are as hollows: (1) Dead space on the gate matrix block can be minimized, (2) the aspect ratio can be controlled finely, (3) since polar graphs are successfully used in the second phase, the efficiency of the algorithm can be much improved. The experimental results show the effectiveness of our algorithm.

A new applicative design language is proposed for developing generators of data-path modules from hardware algorithms. The language includes a set of primitives that represent placement operations, parameterized cells, routing patterns and a set of transformation rules specifying modifications of the module topology without changing its functionality. Using the language, a hardware algorithm designer can easily define both the topological and geometrical specifications of module generation directly at the functional level without engaged in the layout details. A sketch of the language and an example of module design with the language is presented.

We show that, if NP language L has an invulnerable generator and if L has an honest verifier standard statistical ZKIP, then L has a 5 move statistical ZKIP. Our class of languages involves random self reducible languages because they have standard perfect ZKIPs. We show another class of languages (class K) which have standard perfect ZKIPs. Blum numbers and a set of graphs with odd automorphism belong to this class. Therefore, languages in class K have 5 move statistical ZKIPs if they have invulnerable generators.

We developed a 32-bit pseudorandom number generator (RNG) operating at liquid nitrogen temperature based on HEMT ICs. It generates maximum-length-sequence codes whose primitive polynomial is X47+X42+1 with the period of 247-1 clock cycle. We designed and fabricated three kinds of cryogenic HEMT IC for this system: A 1306-gate controller IC, a 3319-gate pseudorandom number generator (RNG) IC, and a buffer IC containing a 4-kb RAM and 514 gates. We used 0.6-µm gate-length Se-doped GaAlAs/GaAs HEMTs. Interconnects were Al for the first layer and Au/Pt/Ti for the second layer with a SiON insulator between them. The HEMT ICs have direct-coupled FET logic (DCFL) gates internally and emitter-coupled logic (ECL) compatible input-putput buffers. The unloaded basic delay of the DCFL gate was 17 ps/gate with a power consumption of 1.4 mW/gate at liquid nitrogen temperature. We used an automatic cryogenic wafer probe we developed and an IC tester for function tests, and used a high-speed performance measuring system we also developed with a bandwidth of more than 20 GHz for high-speed performance tests. Power dissipations were 3.8 W for the controller IC, 4.5 W for the RNG IC, and 3.0 W for the buffer IC. The RNG IC, the largest of the three HEMT ICs, had a maximum operating clock rate of 1.6 GHz at liquid nitrogen temperature. We submerged a specially developed zirconium ceramic printed circuit board carrying the HEMT ICs in a closed-cycle cooling system. The HEMT ICs were flip-chip-packaged on the board with bumps containing indium as the principal component. We confirmed that the RNG system operates at liquid nitrogen temperature and measured a minimum system clock period of 1.49 ns.

An autonatic layout scheme dedicated to bipolar analog modules is described. A layout model is settled in such a way that the VCC/GND line is laid out on top/bottom edge of a rectangular region, within which the whole elements are placed and interconnected. According to this simple modeling, a layout scheme can be constructed of a series of the following algorithms: First clustering is executed for partitioning a given circuit into clusters, each having connections with VCC and GND lines, and then linear ordering is applied to clusters so as to be placed in a one-dimensional array. After a relative placement of circuits elements in each cluster, a block compactor is implemented by means of packing blocks in each cluster into an idle space, and then a detailed router is conducted to attain 100% interconnection. Finally a layout compactor is invoked to pack all layout patterns into a rectangle of the minimum possible area. A number of implementation results are also shown to reveal the practicability of the proposed analog module generator.

A method is presented for analyzing the scalar wave scattering from a conducting target of arbitrary shape in random media for both the Dirichlet and Neumann problems. The current generators on the target are introduced and expressed generally by the Yasuura method. When using the current generators, the scattering problem is reduced to the wave propagation problem in random media.