To maintain blockchain-based services with ensuring its security, it is an important issue how to decide a mining reward so that the number of miners participating in the mining increases. We propose a dynamical model of decision-making for miners using an evolutionary game approach and analyze the stability of equilibrium points of the proposed model. The proposed model is described by the 1st-order differential equation. So, it is simple but its theoretical analysis gives an insight into the characteristics of the decision-making. Through the analysis of the equilibrium points, we show the transcritical bifurcations and hysteresis phenomena of the equilibrium points. We also design a controller that determines the mining reward based on the number of participating miners to stabilize the state where all miners participate in the mining. Numerical simulation shows that there is a trade-off in the choice of the design parameters.

We report the characterization of hysteresis in SOI-based super-steep subthreshold slope FETs, which are conventional floating body and body-tied, and newly proposed PN-body-tied structures. We found that the hysteresis widths of the PN-body-tied structures are smaller than that of the conventional floating body and body-tied structures; this means that they are feasible for switching devices. Detailed characterizations of the hysteresis widths of each device are also reported in the study, such as dependency on the gate length and the impurity concentration.

This paper introduces a hard handover strategy with a novel adaptive hysteresis adjustment that is needed to reduce handover drop rate in 3GPP long term evolution (LTE). First of all, we adopt a Hybrid handover scheme considering both the received signal strength (RSS) and the load information of the adjacent evolved Node Bs (eNBs) as a factor for deciding the target eNB. The Hybrid scheme causes the load status between the adjacent eNBs to be largely similar. Then, we propose a modified load-based adaptive hysteresis scheme to find a suitable handover hysteresis value utilizing the feature of the small load difference between the target and serving eNBs obtained from the result of the Hybrid scheme. As a result, through the proposed modified load-based adaptive hysteresis scheme, the best target cell is very well selected according to the dynamically changing communication environments. The simulation results show that the proposed scheme provides good performance in terms of handover drop rate.

In order to realize stable n-type characteristics of pentacene for applying to the organic complementary metal-oxide-semiconductor field-effect transistors (CMOS), we have fabricated pentacene based MOS diodes using ultra-thin Yb layer such as 0.5-3 nm between gate insulator and pentacene. From the results of capacitance-voltage (C-V) measurements, excellent n-type C-V characteristics of the devices with 1 and 2 nm-thick Yb were observed even though the devices were measured in air. These results suggested that the n-type semiconductor characteristics of pentacene are able to be improved by the thin Yb interfacial layer. Furthermore, the improved n-type characteristics of pentacene will enable the fabrication of flexible complementary logic circuits utilizing one kind organic semiconductor.

A multiple-peak negative differential resistance (NDR) circuit made of standard Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) is demonstrated. We can obtain a three-peak I-V curve by connecting three cascoded MOS-HBT-NDR circuits by suitably designing the MOS parameters. This novel three-peak NDR circuit possesses the adjustable current-voltage characteristics and high peak-to-valley current ratio (PVCR). We can adjust the PVCR values to be as high as 11.5, 6.5, and 10.3 for three peaks, respectively. Because the NDR circuit is a very strong nonlinear element, we discuss the extrinsic hysteresis phenomena in this multiple-peak NDR circuit. The effect of series resistance on hysteresis phenomena is also investigated. Our design and fabrication of the NDR circuit is based on the standard 0.35 µm SiGe BiCMOS process.

MOS capacitors with Si-implanted thermal oxide and CVD deposited oxide of 30 nm thickness were fabricated for applications of non-volatile memory and electroluminescence devices. Current-voltage (I-V) and I-V hysteresis characteristics were measured, and the hysteresis window (HW) and the integrated charge of HW (ICHW) extracted from the hysteresis data were discussed. The HW characteristics of high Si dose samples showed the asymmetrical double-peaks curves with the hump in both tails. The ICHW almost converged after the 4th cycle and had the voltage sweep speed dependence. All +ICHW and -ICHW characteristics were closely related to the static (+I)-(+VG) and (-I)-(-VG) curves, respectively. For the high Si dose samples, the clear hump currents in the static I-VG characteristics contribute to lower the rising voltage and to steepen the ICHW increase, which correspond to the large stored charge in the oxide.

In this study, we propose an adaptive handoff scheme with dynamic hysteresis value for cellular communications, which is based on distance between the mobile station and the serving base station. Performance is evaluated in terms of the expected number of handoffs, the expected handoff delay, standard deviation of handoff location, and the expected link degradation probability as well. Numerical results and simulations show that the proposed scheme outperforms the handoff schemes with static hysteresis levels. The effect of distance error is also discussed.

This paper presents an improved gate drive circuit for high power GTO thyristors. The energy-storage/transfer characteristics of an air-core reactor and the fast switching characteristics of FET are employed to make a high gate current of sharp pulse form. The power loss in the gate drive circuit is reduced by using the low resistance and the hysteresis comparator to detect and control the steady on-gate current. The proposed gate drive circuit is analyzed and its usefulness is confirmed by experiments.

High performance delay-locked loop (DLL) is key to the high data rate chip-to-chip communication, suggesting the output jitter, due to power noise, bang-bang noise, temperature-voltage drift, etc, should be properly controlled. In this paper, high speed DRAM operation can be achieved by a dual loop DLL with various novel techniques; a new counting code with hysteretic bit-transitions can remove the large DAC glitches by preventing the binary bit-transitions in the locking states. A delay buffer, which is insensitive to the power supply fluctuations, is proposed. The voltage-temperature (VT) dependencies of the feedback path and the open clock path are balanced, minimizing the VT shift of the clock. As a result, the high-speed DRAM interface with the maximized setup/hold window can be accomplished.

This paper proposes a new controlling technique of asynchronous sigma delta modulation with characteristic of one-cycle response. This technique can reject power source perturbations in one cycle period and reduce the peaks of harmonic with one side random hysteresis technique. The proposed method was analyzed, designed, and experimented in a full bridge inverter. The distortion of output voltage and the harmonic peaks were used to measure the performance of the proposed technique. The experimental results show that the proposed technique can reduce the peak of harmonic up to 0.42 p.u and the harmonic distortion 5.9% at the ripple of 20% of power source when comparing with convention asynchronous sigma delta modulation.

The carbon nanotube field-effect transistors show the hysteresis characteristic in their electrical characteristics owing to the amorphous carbon around the carbon nanotube. It is shown here the reduction of the hysteresis characteristic by the refining process applied repeatedly to the carbon nanotube. Moreover, after the refining processes, the transconductance of carbon nanotube field-effect transistor becomes 2.0 µS the ten times larger than before the refining process. Almost all carbon nanotubes without the refining processes, grown by thermal chemical vapor deposition, show the p type semiconductor characteristics. After the refining processes on the other hand, almost all carbon nanotube show the ambipolar type semiconductor characteristics.

This paper presents a technique for the variation of hysteresis band in delta-sigma modulation. A sinusoidal, and a random hystersis band are combined to achieve an optimal performance in terms of constant switching frequency and the harmonic spikes. The sinusoidal hysteresis band technique produces a constant switching frequency while the random hysteresis band suppresses the harmonic spikes. The effects of various variations of hysteresis band on the harmonic spectrum characteristic were described. The technique is experimented in a single-phase inverter and the harmonic peaks and the distortion of output voltage were used to measure the performance of the proposed technique.

This letter introduces a chaotic circuit consisting of one linear 2-port VCCS, one hysteresis 2-port VCCS, and two capacitors. The circuit has double screw attractors, quad screw attractors and co-existence states of them. Since the system is piecewise linear, attractors existence condition can be described using exact piecewise solutions. Using a simple test circuit, typical phenomena are verified in the laboratory.

In a previous study about a combinatorial optimization problem solver using neural networks, since the Hopfield method, convergence to the optimum solution sooner and with more certainty is regarded as important. Namely, only static states are considered as the information. However, from a biological point of view, dynamical systems have attracted attention recently. Therefore, we propose a "dynamical" combinatorial optimization problem solver using hysteresis neural networks. In this paper, the proposed system is evaluated by the N-Queen problem.

As two simple relaxation oscillators are coupled by periodical and instantaneous switching, the system exhibits rich superstable synchronous phenomena. In order to analyze the phenomena, we derive a hybrid return map of real and binary variables; and give theoretical results for (1) superstability of the synchronous phenomena and (2) period of the synchronous phenomena as a function of the parameters. Using a simple test circuit, typical phenomena are verified in the laboratory.

We propose hysteresis neural network solving combinatorial optimization problems, Box Puzzling Problem. Hysteresis neural network searches solutions of the problem with nonlinear dynamics. The output vector becomes stable only when it corresponds with a solution. This system does never become stable without satisfying constraints of the problem. After estimating hardware calculating time, we obtain that numerical calculating time increases extremely comparing with hardware time as problem's scale increases. However the system has possibility of limit cycle. Though it is very hard to remove limit cycle completely, we propose some methods to remove this phenomenon.

A behavioral model for ferroelectric capacitors is developed. There are two requirements for the circuit simulation model; one is to reproduce the hysteretic behavior of the polarization under arbitrary voltage history, and the other is to describe the time dependence of polarization change. A parallel element model has been proposed to meet the first requirement. This model reproduces the minor loops of the hysteresis by assuming that the ferroelectric capacitor consists of the parallel capacitors of different polarization and coercive voltages. In order to add the function to describe the time dependence of the polarization change, we propose a method of measuring the switching response for individual parallel elements and the model which describes the response. In the measurement, the voltage applied to the capacitor is raised in two steps. After the first step, the voltage is kept at an intermediate level for a period of time, then raised again to the final level and the polarization change was recorded as a function of time. Because the capacitor elements with the coercive voltage lower than the intermediate level complete switching during the first step, the polarization change of the whole capacitor during the second step is attributed to the capacitor elements with the coercive voltage higher than the intermediate level. This procedure is repeated with changing the intermediate level, and the switching response of each capacitor element is obtained by taking the finite differences between the adjacent sets of data. The measurement on a sol-gel derived SrBi2Ta2O9 capacitor revealed that the switching time depended only on the difference between the applied voltage and the coercive voltage of each capacitor element. The time dependence of the polarization change is implemented to the model by inserting a nonlinear resistor in series with each capacitor, which reproduces the polarization switching under arbitrary voltage change without any fitting parameters.

A 2-step deposition technique was introduced in the heteroepitaxial growth of barium titanate (BaTiO3) thin films. Heteroepitaxial BaTiO3 films were prepared on a SrRuO3/SrTiO3 substrate by radio frequency (RF) magnetron sputtering with three kinds of deposition method: low RF-power deposition, 2-step deposition, and high power deposition. The crystallographic and ferroelectric properties were evaluated for the heteroepitaxial films. When the epitaxial capacitor was prepared by the 2-step deposition technique, the ferroelectric remanent polarization, 2Pr, was maximized. The optimized deposition condition to improve the crystal quality is discussed in terms of damage and diffusion, which could be introduced into the oxide films during the epitaxial growth, and controlled by the RF-power and deposition time, respectively.

We propose a hysteresis neural network system solving NP-Hard optimization problems, the N-Queens Problem. The continuous system with binary outputs searches a solution of the problem without energy function. The output vector corresponds to a complete solution when the output vector becomes stable. That is, this system does never become stable without satisfying the constraints of the problem. Though it is very hard to remove limit cycle completely from this system, we can propose a new method to reduce the possibility of limit cycle by controlling time constants.

The fact that there exists a core sinusoidal oscillator at the heart of Saito's double-screw hysteresis chaotic oscillator is demonstrated. By applying Bruton's transformation to the active linear part of the circuit, which is shown to be a classical LC-R negative resistor sinusoidal oscillator, an inductorless realization based on a frequency-dependent negative resistor (FDNR) is obtained. The LC-R sinusoidal oscillator is replaced by an FDNR-R oscillator. Furthermore, we show that chaotic behaviour can be preserved when a simple minimum component 2R-2C sinusoidal oscillator is used. Two different realizations of the non-monotone current-controlled hysteresis resistor, one of which is completely passive, are investigated. Experimental results of selected circuits, PSpice and numerical simulations are included.