This letter proposes a dynamic phasor-based apparent impedance measuring method for a single-line-to-ground fault. Using the proposed method, the effects of the decaying DC components on the apparent impedance of a single-line-to-ground fault can be completely removed. Compared with previous works, the proposed method uses less computation to measure an accurate apparent impedance.

A planar inverted-E (PIE) antenna that can achieve a wide impedance bandwidth is proposed. The antenna is realized by inserting a branch capacitance between the feed line and the shorting pin of a conventional planar inverted-F antenna (PIFA). Such a modification significantly enhanced the impedance bandwidth while maintaining the antenna size. The proposed antenna possesses a very wide impedance bandwidth of 1250 MHz (1650-2900 MHz) at a voltage standing wave ratio (VSWR) <3. In addition, good radiation patterns were obtained at the desired frequency bands.

We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.

A monolithic modulator driver IC based on InP HBTs with a new circuit topology -- called a functional distributed circuit (FDC) -- for over 80-Gb/s optical transmission systems has been developed. The FDC topology includes a wide-band amplifier designed using a distributed circuit, a digital function designed using a lumped circuit, and broadband impedance matching between the lumped circuit and distributed circuit to enable both wider bandwidth and digital functions. The driver IC integrated with a 2:1 multiplexing function produces 2.6-Vp-p (differential output: 5.2 Vp-p) and 2.4- Vp-p (differential output: 4.8 Vp-p) output-voltage swings with less than 450-fs and 530-fs rms jitter at 80 Gb/s and 90 Gb/s, respectively. To the best of our knowledge, this is equivalent to the highest data rate operation yet reported for monolithic modulator drivers. When it was mounted in a module, the driver IC successfully achieved electro-optical modulation using a dual-drive LiNbO3 Mach-Zehnder modulator up to 90 Gb/s. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over-80-Gb/s transmission systems.

The use of the in-phase synthetic method is proposed for antenna calibration using the three-antenna method (TAM) in order to make the TAM applicable even in a semi-anechoic chamber (SAC) or on an open-area test site. Suitable antenna arrangements are theoretically investigated for this improved calibration method. Experimental analyses demonstrate that the in-phase synthetic method can remarkably reduce unwanted effects of the ground-reflected wave. Therefore, even on a metal ground plane, the proposed TAM with the in-phase synthetic method can yield an accurate actual gain of a double ridged guide antenna at frequencies from 4 GHz to 14 GHz with differences of +0.16/-0.37 dB from the results of the conventional TAM performed in an fully anechoic room (FAR).

Basic left hand mode transmission line (LH mode TL) characteristics made on PCB is an important future issue for the application of the EMC field. In this paper, possibility of a LH mode TL characteristic made by a folded-stepped impedance resonator (F-SIR) type is investigated experimentally and numerically. The experimental and calculated from FEM and equivalent circuit results indicate that some backward propagation characteristic and negative group delay can be established by F-SIR structure.

This paper describes a time-domain expression based on the physical model of power amplifiers where electric memory effect is considered to be caused by even-order nonlinearity and bias impedance. It is demonstrated that the time-domain expression is consistent with the general memory polynomial reported by D.R. Morgan et al. To confirm validity of the physical model, a simple method is proposed to measure amplitude and phase of IMD by two tone test: the phase is extracted from measured small signal S-parameters of the amplifier under test. The method is applied to a GaN FET amplifier under condition that memory effect is enhanced by applying inductive cable for DC supply. Frequency dependent IMD is fitted by a parallel connection of L, C, and R: it has been confirmed that the frequency dependence of IMD is given by the bias impedance at even order harmonics of envelope frequency. The frequency dependence assures the validity of the physical model as well as the time-domain expression.

The design of microstrip bandpass filters using stepped-impedance resonators (SIRs) is examined. The passband center frequency for the WCDMA-FDD (uplink band) Japanese cellular system is 1950 MHz with a 60-MHz bandwidth. The SIR physical characteristic can be designed using a SIR characteristic chart based on second harmonic suppression. In our filter design, passband design charts were obtained through the design procedure. Tchebycheff and maximally flat bandpass filters of any bandwidth and any number of steps can be designed using these passband design charts. In addition, sharp skirt characteristics in the passband can be realized by having two transmission zeros at both adjacent frequency bands by using open-ended quarter-wavelength stubs at input and output ports. A new even-mode harmonics suppression technique is proposed to enable a wide rejection band having a high suppression level. The unloaded quality factor of the resonator used in the proposed filters is greater than 240.

In this study, we use the deconvolution of a square test stimulus to replace a series of sinusoidal test waveforms with different frequencies to simplify the measurement of human body impedance. The average biological impedance of body parts is evaluated by constructing a frequency response of the equivalent human body system. Only two stainless-steel electrodes are employed in the measurement and evaluation.

A swing level controlled voltage-mode transmitter is proposed to support a stub series-terminated logic channel with center-tapped termination. This transmitter provides a swing level control to support the diagnostic mode and improve the signal integrity in the absence of the destination termination. By using the variable parallel termination, the proposed transmitter maintains the constant output impedance of the source termination while the swing level is controlled. Also, the series termination using an external resistor is used to reduce the impedance mismatch effect due to the parasitic components of the capacitor and inductor. To verify the proposed transmitter, the voltage-mode driver, which provides eight swing levels with the constant output impedance of about 50 Ω, was implemented using a 70 nm 1-poly 3-metal DRAM process with a 1.5 V supply. The jitter reduction of 54% was measured with the swing level controlled voltage-mode driver in the absence of the destination termination at 1.6-Gb/s.

In this paper, we utilize low temperature co-fired ceramic technology (LTCC) to realize a modified short-circuited stub bandpass filter suitable for ultra-wideband (UWB) applications. By modifying the conventional short-circuited stub bandpass filter structure with stubs and connecting lines of lower characteristic impedances, the number of stubs has been reduced from 5 to 2 on a high dielectric constant substrate (∈ r = 40). A wireless local area network (WLAN) stopband in the frequency range of 5.15 to 5.825 GHz has been inserted into the filter characteristic using three short-circuited coupled lines. The filter is fabricated and measurement results show that it has an insertion loss less than 1.0 dB and return loss better than 10 dB in the pass bands. A bandwidth ratio of 109.49% has been achieved. Measurement results agree well with simulation results. The dimensions of the filter are 480.57 mm3.

In this paper, a 10-Gb/s CMOS optical receiver analog front-end is designed and implemented in 0.13-µm CMOS technology. An optical receiver analog front-end includes a pre-amplifier and a post amplifier. To ensure 10-Gb/s operation, the effect of inherent photodiode parasitic capacitance should be suppressed. Thus, an advanced common-gate stage is exploited as the input stage of pre amplifier. To enhance the bandwidth without a passive inductor, a new post amplifier with active feedback and negative capacitance compensation techniques is proposed. A prototype chip has 98-dBΩ of trans-impedance gain (ZT), corresponding 40-dB input dynamic range (5-µA to 500-µA) and minimum allowable input current (5-µA). Also, the receiver achieves the bandwidth of 7.5-GHz for 0.25-pF photodiode parasitic capacitance, and the measured optical sensitivity equals -18-dBm for 10-12 bit error rate (BER).

An extreamly large scale periodic array antenna is required for transmitting power from space solar power systems. Analysis of the huge-scale array antenna is important to estimate the radiation property of the array antenna, but a full-wave analysis requires too much computer memory and excessive CPU time. In order to overcome these difficulties, the impedance extension method is proposed as a method of approximate analysis for huge periodic array antennas. From the results of actual gain pattern obtained by the proposed method and its relative error, it is shown that edge effects of a huge-scale array antenna can be ignored in calculating the radiation property.

We carried out degradation analysis of a blue phosphorescent organic light emitting diode by both impedance spectroscopy and transient electroluminescence (EL) spectroscopy. The number of semicircles observed in the Cole-Cole plot of the modulus became three to two after the device was operated for 567 hours. Considering the effective layer thickness of the initial and degraded devices did not change by degradation and combining the analysis of the Bode-plot of the imaginary part of the modulus, the relaxation times of emission layer and hole-blocking with electron transport layers changed to nearly the same value by the increase of the resistance of emission layer. Decay time of transient EL of the initial device was coincident with that of the degraded one. These phenomena suggest that no phosphorescence quenching sites are generated in the degraded device, but the number of the emission sites decrease by degradation.

An inductive buffer peaking technique is proposed and demonstrated to extend the bandwidth of a 10-Gbit/s transimpedance amplifier (TIA) for optical communications. A TIA using this peaking technique is fabricated based on InGaP/GaAs HBT technology. The advantage of the proposed technique is verified by comparisons based on simulations and experiments. For these comparisons, three different types of TIAs using a basic gain stage, a shunt peaking gain stage and the proposed gain stage, respectively, are fabricated and measured. The measured performance of the proposed TIA shows that this bandwidth extension technique using inductive buffer peaking can be applied to circuit designs which demand wideband frequency response with low power consumption.

Electrical modeling for surface-mount passive components is proposed. In order to accurately capture parasitic inductance, the proposed 2-port model accounts for surrounding ground layer configurations of the print circuit board (PCB) on which the component is mounted. Our model retains conventional modeling paradigm in which component suppliers provide their customers with simulation models characterized independently of the customers' PCB. We also present necessary corrections that compensate magnetic coupling between the separated models. Impedance and its anti-resonant frequency of two power distribution networks are experimentally analyzed being non-separated modeling as the reference. The proposed model achieved very good match with the reference result reducing 7-34% error of the conventional model to about 2%.

An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.

In the electromagnetic theory, the vacuum impedance Z0 is a universal constant, which is as important as the velocity of light c0 in vacuum. Unfortunately, however, its significance is not appreciated so well and sometimes the presence itself is ignored. It is partly because in the Gaussian system of units, which has widely been used for long time, Z0 is a dimensionless constant and of unit magnitude. In this paper, we clarify that Z0 is a fundamental parameter in electromagnetism and plays major roles in the following scenes: reorganizing the structure of the electromagnetic formula in reference to the relativity; renormalizing the quantities toward natural unit systems starting from the SI unit system; and defining the magnitudes of electromagnetic units.

An inverse scattering problem of estimating the reflection coefficient and the surface impedance from two sets of absolute values of the near field with periodic change is investigated. The problem is formulated in terms of a nonlinear simultaneous equations which is derived from the relation between the two sets of absolute values and the field defined by a finite summation of the modal functions by applying the Fourier analysis. The reflection coefficient is estimated by solving the equations by Newton's method through the successive algorithm with the increment of the number of truncation in the summation one after another. Numerical examples are given and the accuracy of the estimation is discussed.

In this paper, an alternative approach is presented, to design equalizers (or matching networks) with commensurate (or equal length) transmission lines. The new method automatically yields the matching network topology with characteristic impedances of the commensurate lines. In the implementation process of the new technique first, the driving point impedance data of the matching network is generated by tracing a pre-selected transducer power gain shape, without optimization. Then, it is modelled as a realizable bounded-real input reflection coefficient in Richard domain, which in turn yields the desired equalizer topology with line characteristic impedances. This process results in an excellent initial design for the commercially available computer aided design (CAD) packages to generate final circuit layout for fabrication. An example is given to illustrate the utilization of the new method. It is expected that the proposed design technique is employed as a front-end, to commercially available computer aided design (CAD) packages which generate the actual equalizer circuit layout with physical dimensions for mass production.