This paper proposes a very small on-chip multimedia real-time OS for embedded system LSIs, and demonstrates its usefulness on MPEG-2 multimedia applications. The real-time OS, which has a conditional cyclic task with suspend and resume for interacting hardware (HW) / software (SW) of embedded system LSIs, implements the minimum set of task, interrupt, and semaphore managements on the basis of an analysis of embedded software requirements. It requires only about 2.5 Kbytes memory on run-time, reduces redundant conventional cyclic task execution steps to about 1/2 for HW/SW interactions, and provides sufficient performance in real-time through implementing two typical embedded softwares for practical multimedia system LSIs: an MPEG-2 system protocol LSI and an MPEG-2 video encoder LSI. This on-chip multimedia real-time OS with 2.5 Kbyte memory will be acceptable for future multimedia embedded system LSIs.

This paper proposes a new satellite communication system that enables high-speed communication in a mobile environment. The system configuration combines a terrestrial mobile network and an existing satellite system, and includes a tracking antenna that was newly developed to receive 30 Mbit/s signals from commercial communication satellites. A prototype system comprising the mobile network, the satellite system and a vehicle in which the tracking antenna is installed was constructed for purposes of evaluation and demonstration. A LAN system was incorporated in the experimental vehicle by using the tracking antenna, a satellite router and a Personal Digital Cellular phone. The validity of the proposed system was verified by the tracking antenna driving tests, system UDP tests and FTP throughput tests in a mobile environment.

Currently, the issues in Quality of Service, fairness and pricing strategies should have expedited the emergence of service differentiation in wireless access networks. In this paper, we propose a novel scheduling algorithm, called the Wireless Differentiated Fair Queueing (WDFQ) algorithm, to accommodate such need by providing delay/jitter controls, and fair residual bandwidth sharing for real-time and non-real-time traffic streams simultaneously. We show that the WDFQ scheme can achieve excellent performance, including timely delivery of real-time traffic, virtually error-free transmission of non-real-time traffic, and fair usage of channel bandwidth among remote stations. In addition, the location-dependent channel error property, as appeared in most wireless networks, are considered in the model and the temporary short error bursts are compensated by credits of bandwidth. The simulation results suggest that the length of retransmission period should be adapted to the error length to achieve good performance and maintain low implementation complexity.

Call admission control (CAC) is becoming vital for multimedia services in the ability of wireless/mobile networks to guarantee Quality of Service (QoS) partially due to the network's limited capacity. In this paper, we propose an optimal call admission control scheme with bandwidth reallocation algorithm (multi-class-CAC-BRA) for multi-classes of adaptive multimedia services in wireless/mobile networks. The multi-class-CAC-BRA approach optimizes revenue for service providers and satisfies QoS requirements for service users. The proposed approach adopts semi-Markov Decision Process to model both call admission control and bandwidth reallocation algorithm. In other words, whenever decisions are made, decisions are made for both call admission control and bandwidth reallocation. Since the non-adaptive multimedia traffic is a special case of the adaptive multimedia traffic, the non-adaptive optimal CAC scheme is a special case of our optimal multi-class-CAC-BRA scheme. Furthermore, the Interior-point Method in linear programming is used to solve the optimal decision problem. Simulation results reveal that the proposed multi-class-CAC-BRA scheme adapts itself well to adaptive multi-class multimedia traffic, achieves optimal revenue, and satisfies QoS requirements that are the upper bounds of handoff dropping probabilities. Our approach solves the optimal adaptive multimedia CAC problem. We believe that this work has both theoretical and practical significance.

In software-based wireless multimedia communications systems, each mobile terminal will be able to select its best-suited transmission format according to its quality of service (QoS) and channel condition. In this paper, we focus attention on "access scheme selectability" in such a software-based system, and discuss the traffic performance improvement due to adaptive access scheme selection. Assuming a software-based TDMA/CDMA system where time division multiple access (TDMA) and direct sequence code division multiple access (DS-CDMA) schemes are flexibly selectable, we evaluate the traffic performance in terms of average delay with a typical multimedia service model to be supported in future wireless communications systems. In the TDMA/CDMA system, how to determine an appropriate access scheme for a user is a key issue. Therefore, we discuss the selection algorithm for efficiently supporting heterogeneous multimedia services. Our computer simulation results show that the software-based system with a simple access scheme selection algorithm can significantly improve the traffic performance as compared with conventional hardware-based systems.

A multimedia content is usually read-only and composed of multimedia objects with their spatial and temporal specifications. These specifications given by its author can enforce the display of objects to be well organized for its context. When multimedia contents are serviced in network environment by an on-demand basis, the temporal relationship among the objects can be used to improve the performance of the service. This paper models the temporal relationship as a scenario that represents the presentation order of the objects in a scenario and proposes several scheduling methods that make it possible to rearrange the transmission order of objects in a scenario. As a result, system resources such as computing power and network bandwidth can be highly utilized. Since the temporal relationship of a scenario is static, it is possible to reduce the scheduling overhead of a server by pre-scheduling currently servicing scenarios. In addition, several simulation results are presented in order to compare and analyze the characteristics of the proposed methods.

This paper proposes a media synchronization scheme with causality control for distributed multimedia applications in which the temporal and causal relationships exist among media streams such as computer data, voice, and video. In the scheme, the Δ-causality control is performed for causality, and the Virtual-Time Rendering (VTR) algorithm, which the authors previously proposed, is used for media synchronization. The paper deals with a networked shooting game as an example of such applications and demonstrates the effectiveness of the scheme by experiment.

In this study, we consider a filtering method for image sequence degraded by additive Gaussian noise and/or impulse noise (i.e., mixed noise). For removing the mixed noise from the 1D/2D signal, weighted median filters are well known as a proper choice. We have also proposed a filtering tool based on the weighted median filter with a data-dependent method. We call this data-dependent weighted median (DDWM) filters. Nevertheless, the DDWM filter, its weights are controlled by some local information, is not enough performance to restore the image sequence degraded by the noise. The reason is that the DDWM filter is not able to obtain good filtering performance both in the still and moving regions of an image sequence. To overcome above drawback, we add motion information as a motion detector to the local information that controls the weights of the filters. This new filter is proposed as a Video-Data Dependent Weighted Median (Video-DDWM) filter. Through some simulations, the Video-DDWM filter is shown to give effective restoration results than that given by the DDWM filtering and the conventional filtering method with a motion-conpensation (MC).

This paper proposes three MAC protocols over APON to provide residential and small business customers with multimedia services. The proposed protocols support the frame structure of ITU-T recommendation G.983.1 and also provide diverse ATM service classes such as CBR, rtVBR, nrtVBR, ABR, and UBR traffics. Each service is allocated on the basis of priority. Especially, for allocating CBR and rtVBR services, each protocol uses different cell arrival timing information which is achieved with specific coding and ranging procedure. Focusing the difference of cell arrival timing information, we will investigate the performance of proposed protocols. For the proposed MAC protocols, we present grant field format, minislot format, and bandwidth allocation algorithm. Computer simulation shows the performance of the proposed protocols in terms of CDV and delay, comparing with the normal FIFO protocol.

A 5.6 GOPS/1.4 GFLOPS 350 MHz, four-way very long instruction word (VLIW) microprocessor is developed for embedded applications in a 0.18 µm five-layer-metal CMOS process. This processor features a two-way integer pipeline and two-way floating/media pipelines. Each floating pipeline and media pipeline has two-parallel and four-parallel single instruction multiple-data (SIMD) mechanisms, respectively. The processor has separate instruction and data caches, each of 16 KB in size and having four-way set associative. The data cache employs a non-blocking technique and can process two load instructions in parallel. The processor had about a 50% clock net power reduction compared with one without power optimization. 6.7 million transistors are integrated in an area of 7.5 mm 7.5 mm. Since all circuit blocks were developed using logic synthesis, the processor is easy to adapt to system-on-a-chip (SoC) applications.

This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.

An architectural design of a media processor core optimized for MPEG4/H26x video codec targeted for use in mobile multimedia terminals is presented. The architecture consists of a maximum 6.4 GOPS SIMD (Single Instruction Multiple Data) processor, RISC-processor, VLC-processor, and intelligent DMA controller. The unique SIMD processor completes 2-D DCT processing in 132 clock cycles, or block matching (16 by 16 pixels) in 24 clock-cycles. VLC-processor allows the completion of 8 by 8 block run-level coding in average 10 clock cycles in the case of low bit-rates. The functions of transpose-registers in the SIMD processor, data sub-sampling technique in the DMA, or data-sliding technique between PEs (Processor Elements) in the SIMD processor eliminate a large amount of cycle loss for data handling, and extract the highest level of performance. Through the use of the above architecture and the lower power approach, CIF 30 frames/s MPEG4 Simple Profile video codec @ 100 MHz can be achieved. Estimated dissipation is as low as 280 mW. 300 kgates and 16 kBytes four port SRAM are contained on a 12 mm2 area by using 0.18 µm process technology. The combination of the RISC-processor and SIMD-processor can also operate MPEG4 core profile (shape coding) that requires flexibility and performance.

A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.

A 64-bit architecture for an embedded processor targeted for next-generation digital consumer products has been developed. It has dual-mode instruction sets and is optimized for high multimedia performance, provided by SIMD/floating-point vector instructions in 32-bit length ISA, and small code size, provided by a conventional 16-bit length ISA. Large register files, (6464b and 6432b), a split-branch mechanism, and virtual cache are also adopted in the architecture. A 714MIPS/9.6 GOPS/400 MHz processor core with the 64-bit architecture and a system LSI containing the core are developed using 0.15-µm technology. The LSI includes a 3.2 GB/sec high-bandwidth on-chip bus, a high-speed DRAM interface, a SRAM/Flash/ROM/Multiplexed-bus interface, and a 66 MHz PCI interface that provide the performance required for next-generation multimedia applications.

Nowadays, when people colloquially use the word "wireless," they almost always mean a portable telephone. Over the last 10 years, there has been tremendous growth in the mobile communications markets not only in Japan but also worldwide. For these 10 years, the most popular service has been dominated by voice communication. However, modern mobile communications systems are shifting their focus from solely voice communication to electronic mailing and Internet access. From now, we will evolve into a wireless multimedia society, where a combination of mobile communications and the Internet will play an important role. Wireless technology is the core of mobile communications systems. This article, which focuses on wireless technology, looks at how mobile communications systems have evolved over the last 10 years and looks to the future of advanced wireless technologies that will be necessary to realize a true wireless multimedia society in the coming decade.

For distributed multimedia applications, the development of adaptive QoS (quality of service) management mechanisms is needed to guarantee various and changeable end-to-end QoS requirements. In this paper, we propose an adaptive QoS management framework based on multi-agent systems. In this framework, QoS management mechanisms are divided into two phases, the flow establishment and renegotiation phase and the media-transfer phase. An adaptation to system resource changes and various user requirements is accomplished by direct or indirect collaborations of the agents in each phase. In the flow establishment and renegotiation phase, application agents determine optimal resource allocation with QoS negotiations to maximize the total users' utility. In the media-transfer phase, stream agents collaborate to adjust each stream QoS reactively. In addition, personal agents help a novice user to specify stream QoS without any a priori knowledge of QoS. To make the interworking of agents tractable, a QoS mapping mechanism is needed to translate the QoS parameters from level to level, since the expression of QoS differs from level to level. As an example of multimedia application based on the proposed framework, a one-way video system is designed. The experimental results of computer simulation show the validity of the proposed framework.

A single-chip MPEG-2 video, audio, and system encoder LSI has been developed. It performs concurrent real-time processing of MPEG-2 422P@ML video encoding, 2-channel Dolby Digital or MPEG-1 audio encoding, and system encoding that generates a multiplexed transport stream (TS) or a program stream (PS). Advanced hybrid architecture, which combines a high performance VLIW media-processor D30V and hardwired video processing circuits, has been adopted to satisfy the demands of both high flexibility and enormous computational capability. A unified control scheme has been newly proposed that hierarchically manages adaptive task priority control over asynchronous video, audio, and system encoding processes in order to achieve real-time concurrent processing using a single D30V. Dual dedicated motion estimation cores consisting of a coarse ME core (CME) for wide range searches and a fine ME core (FME) for precise searches have been integrated to produce high picture quality while using a small amount of hardware. Adopting these features, a single-chip encoder has been fabricated using 0.25-micron 4-layer metal CMOS technology, and integrated into a 14.2 mm 14.2 mm die with 11 million transistors.

System capacity of a system consisting of N classes of users is characterized by N-vectors representing the number of users that can be accommodated under a specified BER (bit error rate) constraint in each class. In this paper, system capacity of the reverse link of a wireless multimedia CDMA system with processing gain control is analyzed in the asymptotic regime, when the processing gain G, for receivers with and without CCI cancellers. A new scheme for processing gain control with an optimized power allocation is proposed and its system capacity is compared with the conventional processing gain control scheme as well as the previously discussed power control scheme. It is shown that the proposed scheme has a certain advantage over other schemes.

An aspect of the diverse developments of digital signal processing (DSP) over the last decade are summarized. The current progress of some core fields from the widespread fields are treated in this paper. The selected fields are filter design, wavelet theory and filter bank, adaptive signal processing, nonlinear filters, multidimensional signal processing, intelligent signal processing, and digital signal processor. Through the overview of recent research activities, the interdisciplinary character of the DSP should be proved. Some challenging research direction is described in the last section.

This paper presents a new data hiding scheme under fractal image generation via Fourier filtering method for Computer Graphics (CG) applications. The data hiding operations are achieved in the frequency domain and a method similar to QAM used in digital communication is introduced for efficient embedding in order to explore both phase and amplitude components simultaneously. Consequently, this scheme enables us not only to generate a natural terrain surface without loss of fractalness analogous to the conventional scheme, but also to embed larger amounts of data into an image depending on the fractal dimension. This scheme ensures the correct decoding of the embedded data under lossy data compression such as JPEG by controlling the quantization exponent used in the embedding process.