This paper describes a new method for joining BiSrCaCuO superconductors (BSCCO) which realizes low microwave loss and high mechanical strength. This method consists of two processes. In the first the BSCCO surface is metallized with Ag and in the second a joint is formed by using thermally curable Ag paste. With this method, we obtained a joint with a loss of 0.3 dB around 1.1 GHz with the co-axial cavity techniques. Furthermore, the mechanical strength of the joint was greater than that of the BSCCO sample. From the results of DC resistance measurements and SEM observations, we attribute this good performance to the adhesion and continuity of the metallized Ag with the BSCCO surface.

When intermetal oxide film which contains much water deposited on MOSFET, degradation of hot carrier characteristics is enhanced. This mechanism is considered to be as follows. During the annealing process water is desorbed from the intermetal oxide. The desorbed water reaches the MOSFET and eventually hydrogens terminate silicon dangling bonds in the gate oxide. This paper describes a new approach which uses ESR to analyze this mechanism. The ESR measurement of number of the silicon dangling bonds in undoped polysilicon lying under the intermetal oxide shows that water diffuses from intermetal oxide to MOSFET during the annealing process. The water diffusion is blocked by introduction between the polysilicon and the intermetal oxides of P-SiN layer or CVD SiO2 damaged by implantation.

A 0.25-µm BiCMOS technology has been developed using three sophisticated technologies; the HSST/BiCMOS device, synchrotron orbital radiation (SOR) X-ray lithography, and an advanced two-level metallization. The HSST/BiCMOS provides a 25.4-ps double-poly bipolar device using High-performance Super Self-Aligned Process Technology (HSST), and a 42 ps/2 V CMOS inverter. SOR lithography allows a 0.18 µm gate and 0.2 µm via-hole patternings by using single-level resists. The metallization process features a new planarization technique of the 0.3-µm first wire, and a selective CVD aluminum plug for a 0.25 µm via-hole with contact resistance lower than 1Ω. These 0.25-µm technologies are used to successfully fabricate a 4 KG 0.25 µm CMOS gate-array LSI on a BiCMOS test chip of 12 mm square, which operates at 58 ps/G at 2 V. This result demonstrates that SOR lithography will pave the way for the fabrication of sub-0.25-µm BiCMOS ULSIs.

The dielectric breakdown strength of thermally grown silicon dioxide films was studied for MOS capacitors fabricated on silicon wafers that were intentionally contaminated with magnesium and zinc. Most of magnesium was detected in the oxide film after oxidation. Zinc, some of which evaporated from the surface of wafers, was detected only in the oxide film. The mechanism of the dielectric degradation is dominated by formation of metal silicates, such as Mg2SiO4 (Forsterite) and Zn2SiO4 (Wilemite). The formation of metal silicates has no influence on the generation lifetime of minority carriers, however, it provides the flat-band voltage shift less than 0.3 eV, and forces to increase the density of deep surface states with the zinc contamination.

Via electromigration (EM) performance of aluminum based metallization (AL) systems has been investigated for vias chains of 1500-4000 vias of 1.0 micron diameter. The results show that via EM lifetime can not be enhanced by a simple increase of M2 step coverage in AL/AL vias because the EM induced voids are formed at AL/AL via interface where electrons flow from Ml to M2 even in the case of very poor M2 step coverage. The voids are induced by the boundary layer in AL/AL vias, where a temperature gradient causes discontinuity of aluminum atoms flux. The failure location is not moved though via EM lifetime can be improved by controlling stress in passivation, sputter etch removal thickness and grain size of the first metal. Next, the effect of the boundary layer are eliminated by depositing titanium under the second aluminum or depositing WSi on the first aluminum. In the both cases, via EM lifetime are improved and the failure locations are changed. Especially WSi layer suppresses the voids formation rather than titanium. Models for the failure mechanism in each metallization system are further discussed.

A new effect of barrier metal laid under 1st aluminum layer on electromigration has been found in interconnect vias. This effect can be explained by Si nodules at vias. Stress induced open failure occurred at viaholes and depends on the size of the vias. Stress-migration at vias can be prevented by TiN barrier metal between 1st and 2nd metals. Reliability of electro- and stress-migration at interconnect vias can be explosively improved by using TiN barrier metal.

Copper contamination behavior is studied, depending on the pH level, conductivity type P or N of a silicon substrate, and contamination method of copper. If the pH level of a copper containing solution is adjusted by using ammonia, copper atoms and ammonia molecules produce copper ion complexes. Accordingly, the amount of copper adsorption on the substrate surface is decreased. When N-type silicon substrates are contaminated by means of copper containing solutions, copper atoms on the surfaces diffuse into bulk crystal even at room temperature. But for P-type silicon substrates, copper atoms are transferred into bulk crystal only after high temperature annealing. In the case of silicon substrates contaminated by contact with metallic copper, no copper atom diffusion into bulk crystal was observed. The above mentioned copper contamination behavior can be explained by the charge transfer interaction of copper atoms with silicon substrates.

Breakdown fields and the charges to breakdown (QBD) of oxides increased after UV/Cl2 pre-oxidation cleaning. This is due to decreased residual metal contaminants on silicon surfaces in the bottom of the LOCOS region after wet cleaning. Treatment in NH4OH, H2O2 and H2O prior to UV/Cl2 cleaning suppressed increases in surface roughness and kept leakage currents through the oxides after UV/Cl2 cleaning as low as those after wet cleaning alone. The large junction leakage currents--caused by metal contaminants introduced during dry etching--decreased after UV/Cl2 cleaning which removes the contaminated layer.

An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.

Fiber-optic subscriber loops are beginning to be constructed worldwide as an infrastructure for the 21st century. Making the most of the superior transmission capabilities of optical fiber cable, high-speed and broadband services such as so-called Broadband-ISDN (B-ISDN) services are expected to be achieved. We review current trends in fiber-optic systems and discuss how fiber-optic subscriber loops should be implemented from the points of view of services and technology. First, prospective services offered over fiber-optic subscriber loops and resulting requirements for such loops are presented. Various kinds of services produced through fiber-optic subscriber loops will further develop the information-oriented society and have a major influence not only on the industrial world but on family life as well. Next, basic concepts of totally fiber-optic subscriber loops and proposals for shifting from the existing metallic cable network to totally fiber-optic subscriber loops are discussed. In this regard, we must consider the advantages of optical fiber cables and improve upon the disadvantages of the existing metallic cable network. In particular, a Digital Loop Carrier (DLC) system or a Passive Double Star (PDS) have been proposed to shift from the existing metallic cable network to totally fiber-optic subscriber loops effectively and economically. Finally, line configuration topology and latest fiber-optic technologies such as high-count cable, construction techniques and operation systems for use in achieving totally fiber optic subscriber loops are shown. We believe a single star configuration is the most appropriate for totally fiber-optic subscriber loops.

Among the many fabrication methods for oxide superconductor films, metal organic chemical vapor deposition (MOCVD) is particularly suitable for industrial application because of its mass productivity and the low growth temperature. Therefore we have studied this technique using the horizontal cold wall furnace type MOCVD method to obtain high quality superconducting films. As the result, we have succeeded in fabricating YBa2Cu3Oy films which have high critical temperatures (over 80 K) under substrate temperatures as low as 700 without post-annealing. But, in the course of our experiments, it was found that the thicknesses of YBa2Cu3Oy films fabricated by MOCVD were not uniform. The cause of this non-uniformity is believed to be that the deposition rate exponentially falls off along the flow direction because of the decrease of the source gas concentration through the reaction. In this paper, this non-uniformity is analytically studied. It is shown that the deposition rate decrease can be controlled with a tapered inner tube, and that these theoretical results are in good agreement with the results of experiment. In addition, it is indicated that the superconducting property of the films has less dependence on substrate position as a result of the tapered inner tube.

It is crucial to make Si wafer surfaces ultraclean in order to realize such advanced processes as the low-temperature process and the high-selectivity in the ULSI production. The ultra clean wafer surface must be perfectly free from particles, organic materials, metallic impurities, native oxide, surface microroughness, and adsorbed molecule impurities. Since the metallic contamination on the wafer surface, which is one of the major contaminants to be overcome in order to come up with the ultra clean wafer surface, has the fatal effect on the device characteristics, the metallic impurities in the wafer surface must be suppressed at least below 1010 atoms/cm2. Meanwhile the current dry processes such as reactive ion etching or ion implantation, suffer the metallic contamination of 10121013 atoms/cm2. The wet process becomes increasingly important to remove the metallic impurities introduced in the dry process. Employing a new evaluation method, the metallic impurity segregations at the inrerface between the Si and liquid employed in the wet cleaning process of the Si surface such as ultrapure water and various clemicals were studied. This article clearly indicate that it is important to suppress the metallic impurities, such as Cu, which can exchange electrons with Si to be segregated, at least below the 10 ppt level in ultrapure water and liquid chemical such as HF, H2O2, which are employed in the final step of the wet cleaning. When the ultrapure water rinsing is performed in the ambience containing oxygen, the native oxide grows accompanying an inclusion of metals featuring lower electron negativity than Si. It is revealed that, in order to provent the metallic impurity precipitation, it is require not only to remove metallic impurities from ultrapure water but also to keep the cleaning ambience without oxygen, such as the nitrogen ambience, so as to suppress the native oxide formation.