Various effective and draft legislations and rules in Europe (WEEE--Waste Electrical and Electronic Equipment ROHS--Restrictions on the use of certain substances and ELV--End of life of vehicles) and Japan (Recycling Law for Home Electric Appliances) have either targeted restrictions or fully banned on the use of lead, to be enforced from 2001, 2003 and 2006 onwards. Up to now, mainly tin-lead alloys have been used in electronics. The process temperatures usually applied have been in the range of 230. All currently discussed lead-free alternatives for professional electronics need process temperatures which are at least 20 higher. In addition, the process duration is significantly longer. The combination of higher process temperatures and longer duration results in significant thermal stress on electromechanical devices. In particular the precision mechanics of electromechanical relays must withstand the solder process with maximum process temperatures of 255 without dimensional changes. During the transition from tin-lead to lead-free solder processes all combinations of component surfaces and solder must be possible. The selection of pure Sn100 or SnCu0.7 as terminal surface allows mixed assemblies with tin-lead as well as lead-free solders. All tested combinations of terminal surface, PCB surface and solder showed good results. From these results it can be concluded that mixed assemblies are possible during the transition time without any negative impact on the reliability of the electronic devices.

A 2-dimensional cylindrical k-within-consecutive-(r, s)-out-of-(m, n):F system consists of m n components arranged on a cylindrical grid. Each of m circles has n components, and this system fails if and only if there exists a grid of size r s within which at least k components are failed. This system may be used into reliability models of "Feelers for measuring temperature on reaction chamber," "TFT Liquid Crystal Display system with 360 degree wide area" and others. In this paper, first, we propose an efficient algorithm for the reliability of a 2-dimensional cylindrical k-within-consecutive-(r, s)-out-of-(m, n):F system. The feature of this algorithm is calculating their system reliabilities with shorter computing time and smaller memory size than Akiba and Yamamoto. Next, we show some numerical examples so that our proposed algorithm is more effective than Akiba and Yamamoto for systems with large n.

We propose a new protocol to achieve fault recovery of multicast applications in IP internetwork with mobile participators. Our protocol uses the basic unicast routing capability of IETF Mobile IP as the foundation, and leverages existing IP multicast models to provide reliable multicast services for mobile hosts as well. We believe that the resulting scheme is simple, scalable, transparent, and independent of the underlying multicast routing facility. A key feature of our protocol is the use of multicast forwarding agent (MFA) to address the scalability and reliability issues in the reliable mobile multicast applications. Our simulation results show the distinct performance advantages of our protocol using MFAs over two other approaches proposed for the mobile multicast service, namely Mobile Multicast Protocol (MoM) and bi-directional tunneling, particularly as the number of mobile group members and home agents (HAs) increases.

This study addresses the problem of computing the reliability of stochastic binary systems. This computational problem is known as the problem of the union of a set of events, where each event is expressed as the product of a set of Boolean variables. It is assumed that each Boolean variable may take on either of two states: operative or failed. Computing the reliability of stochastic binary systems is known to be #P-complete. The computation remains #P-complete, even when all events have a cardinality two, and both elements of each event are selected from two disjoint sets. This study proposes a linear time algorithm to compute the reliability of stochastic binary systems when the events satisfy specific requirements.

Marginal reliability importance (MRI) of a component in a system is defined as the rate at which the system reliability changes over changes of the component reliability. MRI helps network designers to construct a reliable network layout. We consider a problem to compute MRI of all components in a network system considering all-terminal reliability in order to rank the components with respect to MRI. The problem is time-consuming since computing network reliability is #P-complete. This paper improves the traditional approach for the problem to proposes an efficient algorithm. The algorithm applies some network transformations, three network reductions and one network decomposition. We have proved lemmas with respect to the relationship between the transformations and MRI, which compute MRI for an original network by using MRI and reliability for transformed networks. Additionally, we have derived a deformed formula to compute MRI, which can also reduce computational task. Numerical experiments revealed that the proposed algorithm reduced computational time considerably compared to the traditional approach.

A negative thermal expansion ceramic substrate and an athermal fiber Bragg grating component with the substrate were subjected to reliability tests. We confirmed that the component has adequate durability for use as optical filters in the WDM system, under test conditions of damp heat, low temperature, mechanical shock and vibration. (50 words)

The explosive growth of the Web contents has led to increasing attention on two major challenges: scalability and high availability of network file system. In this paper, based on our previous reports, we introduced the concept of intermediate file handle to cover the heterogeneity of file system and proposed a new data consistency scheme to reduce the overhead of write request in the reliable network file system. In addition, we also proposed a simple load-sharing mechanism for NFS client to switch to a lightly-load server in order to improve the response time of READ requests. With such an approach, NFS Clients are always active. They issued their requests and waited the corresponding replies. Finally, we analyzed the new data consistency scheme. It shows truly that the scheme is able to improve the performance of our network file system

Several reliability based code search algorithms for maximum likelihood decoding have been proposed. These algorithms search the most likely codeword, using the most reliable information set where the leftmost k (the dimension of code) columns of generator matrix are the most reliable and linearly independent. Especially, D. Gazelle and J. Snyders have proposed an efficient decoding algorithm and this algorithm requires small number of candidate codewords to find out the most likely codeword. In this paper, we propose new efficient methods for both generating candidate codewords and computing metrics of candidate codewords to obtain the most likely codeword at the decoder. The candidate codewords constructed by the proposed method are identical those in the decoding algorithm of Gazelle et al. Consequently, the proposed decoding algorithm reduces the time complexity in total, compared to the decoding algorithm of Gazelle et al. without the degradation in error performance.

This work presents the results of an extensive DC current aging and failure analysis carried out on blue InGaN/GaN LEDs which identify failure mechanisms related to package degradation, changes in effective doping profile, and generation of deep levels. DLTS and ElectroLuminescence (EL) spectra indicate the creation of extended defects in devices aged at very high current density.

Software certification is a notoriously difficult problem. From software reliability engineering perspective, certification process must provide evidence that the program meets or exceeds the required level of reliability. When certifying the reliability of a high assurance system very few, if any, failures are observed by testing. In statistical estimation theory the probability of an event is estimated by determining the proportion of the times it occurs in a fixed number of trials. In absence of failures, the number of required certification tests becomes impractically large. We suggest that subjective reliability estimation from the development lifecycle, based on observed behavior or the reflection of one's belief in the system quality, be included in certification. In statistical terms, we hypothesize that a system failure occurs with the hypothesized probability. Presumed reliability needs to be corroborated by statistical testing during the reliability certification phase. As evidence relevant to the hypothesis increases, we change the degree of belief in the hypothesis. Depending on the corroboration evidence, the system is either certified or rejected. The advantage of the proposed theory is an economically acceptable number of required system certification tests, even for high assurance systems so far considered impossible to certify.

Given the importance of the traffic on modern communication networks, advanced error correction methods are needed to overcome the changes expected in channel quality. Conventional countermeasures that use high dimensionality parity codes often fail to provide sufficient error correction capability. We propose a parity code with high dimensionality that is iteratively decoded. It provides better error correcting capability than conventional decoding methods. The proposal uses the steepest descent method to increase code bit reliability and the coherency between parities and code bits gradually. Furthermore, the quantization of the decoding algorithm is discussed. It is found that decoding with quantization can keep the error correcting capability high.

This paper proposes a novel CMOS built-in current sensor (BICS) for on-line current testing. Proposed BICS detects abnormal current in circuit under test (CUT) and makes a Pass/Fail signal through comparison between the CUT current and the duplicated inverter current. This circuit consists of two current-to-voltage conversion transistors, a full swing generator, a voltage comparator, and an inverter block. It requires 16 transistors. Since this BICS does not require the extra clock, the added extra pin is only one output pin. Furthermore, the BICS does not require test mode selection. Therefore the BICS can be applied to on-line current testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When the CUT is an 8 8 parallel multiplier, the area overhead of the BICS is about 4.34%.

The effect of the silicone vapor on the reliability of the micro-motor was examined. Adsorbed silicone was decomposed to SiO2 by heating due to the discharge between brush and commutator surface. It was found that the operation time until the failure was extremely shortened by the formation of SiO2. The existence of the maximum operation time until the failure was found as depending on the number of revolution. For the higher revolution, many amounts of SiO2 accumulated by the decomposition of the silicone shorten the operation time. For lower revolution, as the torque of the motor reduces, the operation time also shortens. Therefore, the maximum operation time exists for optimum revolution.

An exact and an approximated reliabilities of a 2-dimensional consecutive k-out-of-n:F system are discussed. Although analysis to obtain exact reliability requires many calculation resources for a system with a large number of components, the proposed method obtains the reliability lower bound by using a combinatorial equation that does not depend on the system size. The method has an assumption on the maximum number of failed components in an operable system. The reliability is exact when the total number of failed components is less than the assumed maximum number. The accuracy of the method is confirmed by numerical examples.

This paper presents an efficient application of hot-carrier reliability simulation to delay libraries of 0.18µm and 0.14µm gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products were screened to check whether the rise time restrictions were met. At 200MHz, maximum rise time (0-100%) triseMAX was 0.8nsec (17% of duty) under Δtd/td = 5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.

Ring networks have been extensively studied and installed for communication services. In actual ring networks, nodes are usually allocated at random positions. Two nodes separated far from each other along the route of a ring network may be physically allocated near each other. Adding a supplementary link directly connecting such nodes can shorten the connection paths between the two nodes as well as between other neighboring node pairs. Aggregated length of connection paths of the network can be reduced. Although such a network can be regarded as being composed of two small ring networks sharing the supplementary link, we regarded the network as being modified from a single regular ring network by adding a supplementary link, and thus we quantitatively evaluated the effect of the network modification. We analyzed, for the first time, number of connection paths in the links of networks with or without a supplementary link. A full-mesh topology was assumed, and two types of connection were examined: a single-path and a 2-path connection. The results of this analysis were then used to evaluate system costs and reliability of the networks. The evaluation confirmed that adding a supplementary link is effective in terms of cost reduction and reliability improvement under certain conditions.

Three-dimensional MEMS optical switches(3D-MEMS) and planar lightwave circuit thermo-optical switches (PLC-TOSW) are suitable for use in large-scale photonic cross-connect switches (PXCs). Usually, such large-scale optical switches are created by integrating many small switch elements (such as 12 switches). Therefore, the reliability or lifetime of the individual switch element greatly affects the reliability of the PXC system. In this paper, the effect of the number and failure probability of switch elements on PXC reliability is statistically estimated. First, the equivalent number of switch elements needed to compose a large-scale PXC is determined for the switch types mentioned above. Based on this evaluation, yields and lifetimes of switch modules are estimated for each switch type. The improvement in reliability due to switch duplication (preparing spare switches) is also estimated and discussed.

Consider an undirected graph G=(V,E) with n (=|V|) vertices and m (=|E|) edges. It is well-known that the problem of computing the sequence Nn-1,Nn,...,Nm is #P-complete (see e.g.,[3]), where Ni denotes the number of connected spanning subgraphs with i (n-1!im) edges in G. In this paper, by proving new inequalities on the sequence Nn-1,Nn,...,Nm, we show an interesting and stronger property that the sequence γn-1,γn,...,γm, where γi denotes the average number of spanning trees in the connected spanning subgraphs with i edges, is a convex sequence as well as a monotonically increasing sequence, although this property does not hold for the sequence Nn-1,Nn,...,Nm.

We propose a method to realize soft-decision decoding for hard-detected signals. In this paper, a novel concept is introduced as "error-detected reliability. " The method is very useful for optical fiber communications (OFC) as hard detection is the only detection method for the OFC systems. We demonstrate our proposed method using the turbo code in which soft information is required for decoding. As a result, the simulation shows slight difference in the range of moderate to high signal-to-noise ratio between the proposed decoding scheme and the conventional turbo decoding scheme. Moreover, the bit error rate of 10-11 can be achieved by serial concatenation of a Reed-Solomon code and a turbo code for Q-factor lower than 8.0 dB with a bandwidth expansion ratio of 33.3%.

Low-temperature poly-Si thin film transistor with gate-overlapped LDD (GOLD) structure was fabricated. Reliability was evaluated using electrical stress method comparing conventional LDD and single drain structures. As previous researchers have reported, we have confirmed that the degradation of ON current and the field effect mobility was very small compared to conventional LDD or non-LDD structures. We have analyzed the reliability of the GOLD TFT using two-dimensional device simulator. We have clarified that vertical negative field plays a dominant role for improving the reliability in the GOLD TFT. Impact ionization occurs far from the interface between the oxide and poly-silicon by the vertical negative field. GOLD structure is promising for the realization of system on panel.